P. Cavallera, P. Girard, C. Landrault, S. Pravossoudovitch
{"title":"Delay fault propagation in synchronous sequential circuits","authors":"P. Cavallera, P. Girard, C. Landrault, S. Pravossoudovitch","doi":"10.1109/ATS.1994.367259","DOIUrl":"https://doi.org/10.1109/ATS.1994.367259","url":null,"abstract":"The main task of the fault simulation process is to manage the propagation of the fault effects through the circuit. This paper addresses the problem of propagating gate delay faults in synchronous sequential circuits. The rules for propagating such gate delay faults without any restriction on their size and without considering explicitly the fault size, will be established in this paper. These propagation rules are the foundations of the fault simulator we are developing. This fault simulator will be suitable for simulating gate delay fault in synchronous sequential circuits whatever the fault size may be.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116123119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Boolean process-an analytical approach to circuit representation","authors":"Y. Min","doi":"10.1109/ATS.1994.367223","DOIUrl":"https://doi.org/10.1109/ATS.1994.367223","url":null,"abstract":"One of the most important and challenging problems in today's VLSI design is that of incorporating performance factors in the physical and logical design of VLSI circuits. In order to precisely describe circuit timing behavior, an analytical approach is introduced in this paper. A Boolean process is defined, which is a family of Boolean variables relevant to the time parameter t. A real-valued sample of a Boolean process is a waveform. Any waveform is an expression of a basic waveform. The edge sequence of a waveform is represented by a ladder function. This analytical approach enables us to describe the circuit timing behavior in an accurate way, and is applicable to IC design and test. Interestingly, it is suggested that a test pair with multiple transition might be efficient for delay testing if the initial delay can be controlled.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134285665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}