Boolean process-an analytical approach to circuit representation

Abstract

One of the most important and challenging problems in today's VLSI design is that of incorporating performance factors in the physical and logical design of VLSI circuits. In order to precisely describe circuit timing behavior, an analytical approach is introduced in this paper. A Boolean process is defined, which is a family of Boolean variables relevant to the time parameter t. A real-valued sample of a Boolean process is a waveform. Any waveform is an expression of a basic waveform. The edge sequence of a waveform is represented by a ladder function. This analytical approach enables us to describe the circuit timing behavior in an accurate way, and is applicable to IC design and test. Interestingly, it is suggested that a test pair with multiple transition might be efficient for delay testing if the initial delay can be controlled.<>