Testability considerations in technology mapping

Abstract

We consider the problem of incorporating testability into the process of technology mapping. We demonstrate through examples that the testability of technology mapped circuits depends on the technology mapping process, and can be controlled during this process. We then introduce the required concepts to perform technology mapping with testability considerations. We propose a specific technology mapping procedure that accommodates testability as a criterion for selecting the mapping, and present experimental results to demonstrate the tradeoff between area and testability. We also propose a Design-For-Testability procedure that can be incorporated into the technology mapping procedure, and can guarantee complete fault coverage.<>