Design verification by using universal test sets

Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI:10.1109/ATS.1994.367221

Beyin Chen, Chong Len Lee, J. Chen

引用次数: 9

Abstract

In this paper, the application of universal test sets (UTS) to design verification is studied. First, the paper analyzes the relationships between the design error models and the stuck-at fault model. Then theorems are presented to show that the UTS can detect almost all the design errors. Experimental results show that design verification using UTS is an efficient approach.<>

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使用通用测试集进行设计验证

本文研究了通用测试集在设计验证中的应用。首先，分析了设计误差模型与卡滞故障模型之间的关系。然后给出定理，证明UTS可以检测出几乎所有的设计误差。实验结果表明，利用UTS进行设计验证是一种有效的方法

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of IEEE 3rd Asian Test Symposium (ATS)

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