A unified model for inter-gate and intra-gate CMOS bridging fault: the configuration ratio

Abstract

In order to simulate the effects of a bridging fault it is necessary to accurately determine the intermediate voltage of the shorted nodes and compare it to the logic threshold voltage of the driven gates. This paper presents a general model called "the configuration ratio model" which can be used to determine if a particular structure of transistors gives an intermediate voltage which is higher or lower than a given threshold voltage. This general model applies to inter-gate and intra-gate bridging fault. Moreover the approach is extremely faster than the previous ones since no SPICE simulation is required. The accuracy is of 0.06 V to compare with SPICE simulations.<>