Hardware-accelerated parallel-pattern/multiple-fault-propagation concurrent fault simulation

Abstract

The Munich Simulation Computer, a highly-parallel system, has been an approach to speed up logic simulation. Most recent work, presented in this paper, has been devoted to hardware-accelerated concurrent fault simulation. By the new parallel-pattern/multiple-fault-propagation algorithm, a MuSiC version with 256 processing units can offer a simulation performance of 10/sup 8/ test-vectors times gates evaluated per second.<>