{"title":"内置自测试方法,用于中到高分辨率数模转换器","authors":"Karim Arabi, B. Kaminska, J. Rzeszut","doi":"10.1109/ATS.1994.367203","DOIUrl":null,"url":null,"abstract":"A test approach and circuitry suitable for built-in self-test (BIST) of medium to high-resolution digital-to-analog (D/A) converter are described. Offset, gain, linearity and differential linearity errors are tested without using mixed-mode or logic test equipment. The proposed BIST structure presents a compromise between test cost, area overhead and test time. The BIST circuitry has been designed using CMOS 1.2 /spl mu/m technology. The simulations performed show that the BIST is applicable for testing D/A converters up to 16-bits resolution. By a minor modification the test structure would be able to localize the fail situation and to test all D/A converters on the chip.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"30 2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A built-in self-test approach for medium to high-resolution digital-to-analog converters\",\"authors\":\"Karim Arabi, B. Kaminska, J. Rzeszut\",\"doi\":\"10.1109/ATS.1994.367203\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A test approach and circuitry suitable for built-in self-test (BIST) of medium to high-resolution digital-to-analog (D/A) converter are described. Offset, gain, linearity and differential linearity errors are tested without using mixed-mode or logic test equipment. The proposed BIST structure presents a compromise between test cost, area overhead and test time. The BIST circuitry has been designed using CMOS 1.2 /spl mu/m technology. The simulations performed show that the BIST is applicable for testing D/A converters up to 16-bits resolution. By a minor modification the test structure would be able to localize the fail situation and to test all D/A converters on the chip.<<ETX>>\",\"PeriodicalId\":182440,\"journal\":{\"name\":\"Proceedings of IEEE 3rd Asian Test Symposium (ATS)\",\"volume\":\"30 2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-11-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of IEEE 3rd Asian Test Symposium (ATS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.1994.367203\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.1994.367203","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A built-in self-test approach for medium to high-resolution digital-to-analog converters
A test approach and circuitry suitable for built-in self-test (BIST) of medium to high-resolution digital-to-analog (D/A) converter are described. Offset, gain, linearity and differential linearity errors are tested without using mixed-mode or logic test equipment. The proposed BIST structure presents a compromise between test cost, area overhead and test time. The BIST circuitry has been designed using CMOS 1.2 /spl mu/m technology. The simulations performed show that the BIST is applicable for testing D/A converters up to 16-bits resolution. By a minor modification the test structure would be able to localize the fail situation and to test all D/A converters on the chip.<>