硬件加速并行模式/多故障传播并发故障仿真

Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI:10.1109/ATS.1994.367261

W. Hahn, A. Hagerer

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引用次数: 0

摘要

慕尼黑仿真计算机作为一种高度并行的系统，已经成为提高逻辑仿真速度的一种途径。最近的研究主要集中在硬件加速并发故障仿真方面。通过新的并行模式/多故障传播算法，具有256个处理单元的MuSiC版本可以提供每秒评估10/sup 8/测试向量次门的模拟性能。

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Hardware-accelerated parallel-pattern/multiple-fault-propagation concurrent fault simulation

The Munich Simulation Computer, a highly-parallel system, has been an approach to speed up logic simulation. Most recent work, presented in this paper, has been devoted to hardware-accelerated concurrent fault simulation. By the new parallel-pattern/multiple-fault-propagation algorithm, a MuSiC version with 256 processing units can offer a simulation performance of 10/sup 8/ test-vectors times gates evaluated per second.<>

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Proceedings of IEEE 3rd Asian Test Symposium (ATS)

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