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2009 IEEE International Conference on Microelectronic Test Structures最新文献

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Demonstration of a Sub-micron Damascene Cu/Low-k Mechanical Sensor to Monitor Stress in BEOL Metallization 亚微米Damascene Cu/Low-k机械传感器在BEOL金属化过程中的应力监测演示
2009 IEEE International Conference on Microelectronic Test Structures Pub Date : 2009-04-14 DOI: 10.1109/ICMTS.2009.4814604
Christopher J. Wilson, K. Croes, Zs. Tokei, Gerald Beyer, A. Horsfall, Anthony O'Neill
{"title":"Demonstration of a Sub-micron Damascene Cu/Low-k Mechanical Sensor to Monitor Stress in BEOL Metallization","authors":"Christopher J. Wilson, K. Croes, Zs. Tokei, Gerald Beyer, A. Horsfall, Anthony O'Neill","doi":"10.1109/ICMTS.2009.4814604","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814604","url":null,"abstract":"This work reports the results of a mechanical sensor to monitor stress in 100 nm critical dimension Cu interconnects. Existing methodology developed for larger scale Al sensors is discussed and evaluated for Cu/SiO2 and Cu/Low-k integration schemes. New sensor release methods are then developed and the Cu sensor is demonstrated in single and dual damascene technology. We also demonstrate the sensor is sensitive to process modifications and a viable tool for monitoring stress in the Cu back end of line stack.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127515893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Measurement of MOSFET C-V Curve Variation Using CBCM Method 用CBCM法测量MOSFET C-V曲线变化
2009 IEEE International Conference on Microelectronic Test Structures Pub Date : 2009-04-14 DOI: 10.1109/ICMTS.2009.4814615
K. Tsuji, K. Terada, T. Nakamoto, T. Tsunomura, A. Nishida
{"title":"Measurement of MOSFET C-V Curve Variation Using CBCM Method","authors":"K. Tsuji, K. Terada, T. Nakamoto, T. Tsunomura, A. Nishida","doi":"10.1109/ICMTS.2009.4814615","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814615","url":null,"abstract":"The test circuit, in which the cells including CBCMs (Charge-Based Capacitance Measurements) are arrayed in matrix shape, is developed to measure MOSFET capacitance variation. By adjusting the bias condition of the test circuit, it is able to obtain C-V curves for many MOSFETs. Additionally, a variation of threshold voltage is extracted from the estimated C-V curve variation. The obtained threshold voltage variations are close to those which are obtained from current-voltage characteristics.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116756615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Benefit of Direct Charge Measurement (DCM) on Interconnect Capacitance Measurement 直接充电测量(DCM)对互连电容测量的好处
2009 IEEE International Conference on Microelectronic Test Structures Pub Date : 2009-04-14 DOI: 10.1109/ICMTS.2009.4814644
Yasuhiro Miyake, M. Goto
{"title":"Benefit of Direct Charge Measurement (DCM) on Interconnect Capacitance Measurement","authors":"Yasuhiro Miyake, M. Goto","doi":"10.1109/ICMTS.2009.4814644","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814644","url":null,"abstract":"This paper discusses application of direct charge measurement (DCM) on characterizing on-chip interconnect capacitance. Measurement equipment and techniques are leveraged from Flat Panel Display testing. On-chip active device is not an essential necessity for DCM test structure and it is easy to implement parallel measurements. Femto-Farad measurement sensitivity is achieved without having on-chip active device. Measurement results of silicon and glass substrates, including parallel measurements, are presented.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130035927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Application of Matching Structures to Identify the Source of Systematic Dimensional Offsets in GHOST Proximity Corrected Photomasks 匹配结构在GHOST接近校正光掩模系统尺寸偏移源识别中的应用
2009 IEEE International Conference on Microelectronic Test Structures Pub Date : 2009-04-14 DOI: 10.1109/ICMTS.2009.4814609
S. Smith, A. Tsiamis, M. Mccallum, A. Hourd, J. Stevenson, A. Walton
{"title":"Application of Matching Structures to Identify the Source of Systematic Dimensional Offsets in GHOST Proximity Corrected Photomasks","authors":"S. Smith, A. Tsiamis, M. Mccallum, A. Hourd, J. Stevenson, A. Walton","doi":"10.1109/ICMTS.2009.4814609","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814609","url":null,"abstract":"The effects of the GHOST proximity correction process on chrome-on-quartz photomasks can prove difficult to quantify and so they are not routinely characterised. This paper presents a methodology for addressing this issue using electrical test structures designed to measure dimensional mismatch. In the past these have been used successfully to characterise standard GHOSTed photomasks, which displayed systematic offsets that were not seen on an unGHOSTed mask using the same design. In order to investigate this further, a second mask was fabricated using a variation of the GHOST process which increased the resolution of the secondary exposure to be the same as the primary pattern. This enabled the source of the previously observed systematic offset to be determined as test structures on the new mask did not show the same overall dimensional bias. However, the range of mismatch in some of the structures was increased as a result of the new process.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133132435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
4K-cells Resistive and Charge-Base-Capacitive Measurement Test Structure Array (R-CBCM-TSA) for CMOS Logic Process Development, Monitor and Model 用于CMOS逻辑工艺开发、监控和建模的4k单元电阻和电荷基电容测量测试结构阵列(R-CBCM-TSA)
2009 IEEE International Conference on Microelectronic Test Structures Pub Date : 2009-04-14 DOI: 10.1109/ICMTS.2009.4814645
K. Doong, Keh-Jeng Chang, S.C. Lin, H. Tseng, Akis Dagonis, S. Pan
{"title":"4K-cells Resistive and Charge-Base-Capacitive Measurement Test Structure Array (R-CBCM-TSA) for CMOS Logic Process Development, Monitor and Model","authors":"K. Doong, Keh-Jeng Chang, S.C. Lin, H. Tseng, Akis Dagonis, S. Pan","doi":"10.1109/ICMTS.2009.4814645","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814645","url":null,"abstract":"To maximize the design efficiency of the test chip area and maintain the high accuracy measurement requirement of resistors and capacitors, a 4K-cells resistive and charge-base capacitive test structure array is designed for CMOS logic process development, monitor and model. The test chip utilizes 4-terminal (one of 4 is strongly grounded) Kelvin force/sense measurement for resistive-type and charge-base capacitance measurement (CBCM) for capacitive-type test structures. With the aid of memory-addressing design scheme, any one of the device-under-test in an array can be randomly or sequentially selected for testing with all of them sharing a common probe pad group. To accelerate the testing speed, the address control signals of 8 test structure array are connected in parallel for synchronized parallel testing. A 32×16×8 test structure array has been implemented by utilizing a state-of-the-art logic process to demonstrate design feasibility. The results confirm the excellence of this architecture in measurement with 0.1fF for capacitive and 0.1 ohm for resistive systematic errors, and 7 times testing speed improvement.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123969911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Application of a Micromechanical Test Structure to the Measurement of Stress in an Electroplated Permalloy Film 微机械测试结构在电镀坡莫合金薄膜应力测量中的应用
2009 IEEE International Conference on Microelectronic Test Structures Pub Date : 2009-04-14 DOI: 10.1109/ICMTS.2009.4814614
S. Smith, N. Brockie, J. Terry, N. Wang, A. Horsfall, A. Walton
{"title":"Application of a Micromechanical Test Structure to the Measurement of Stress in an Electroplated Permalloy Film","authors":"S. Smith, N. Brockie, J. Terry, N. Wang, A. Horsfall, A. Walton","doi":"10.1109/ICMTS.2009.4814614","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814614","url":null,"abstract":"Suspended microrotating test structures designed to measure the stress in thin, surface micromachined films have been applied to the production of thick layers of electroplated permalloy (NiFe alloy). This process has particular significance to the production of magnetic MEMS components and devices. It is extremely important to characterise the stress in such materials, especially where these films are to be used on wafers with underlying integrated circuitry as it is well known that the matching of transistors can be affected by mechanical strains induced by interconnect features running above them. A new test chip has been designed and fabricated in order to determine the optimum dimensions for permalloy stress sensor structures.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130775835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Extracting Resistances of Carbon Nanostructures in Vias 孔中碳纳米结构的电阻提取
2009 IEEE International Conference on Microelectronic Test Structures Pub Date : 2009-04-14 DOI: 10.1109/ICMTS.2009.4814603
W. Wu, S. Krishnan, K. Li, Xuhui Sun, Raymond Wu, Toshishige Yamada, Cary Y. Yang
{"title":"Extracting Resistances of Carbon Nanostructures in Vias","authors":"W. Wu, S. Krishnan, K. Li, Xuhui Sun, Raymond Wu, Toshishige Yamada, Cary Y. Yang","doi":"10.1109/ICMTS.2009.4814603","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814603","url":null,"abstract":"This paper describes a current-sensing technique to extract the resistances of carbon nanostructures in via interconnects. Test structures designed and fabricated for via applications contain carbon nanofiber (CNF)-metal composites embedded in silicon dioxide (SiO2). Electrical characterization of single CNFs is performed using an atomic force microscope (AFM). This technique yields a metal-CNF contact resistance of 6.4 k¿ and a lowest CNF resistivity of 1.89e-4 ¿-cm.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"1994 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123761456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
In-Situ Silicon Integrated Tuner for Automated On-Wafer MMW Noise Parameters Extraction using Multi-Impedance Method for Transistor Characterization 利用多阻抗法对晶体管特性进行毫米波噪声参数自动提取的原位硅集成调谐器
2009 IEEE International Conference on Microelectronic Test Structures Pub Date : 2009-04-14 DOI: 10.1109/ICMTS.2009.4814637
Y. Tagro, D. Gloria, S. Boret, Y. Morandini, G. Dambrine
{"title":"In-Situ Silicon Integrated Tuner for Automated On-Wafer MMW Noise Parameters Extraction using Multi-Impedance Method for Transistor Characterization","authors":"Y. Tagro, D. Gloria, S. Boret, Y. Morandini, G. Dambrine","doi":"10.1109/ICMTS.2009.4814637","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814637","url":null,"abstract":"In this paper, for the first time, Silicon integrated tuner is presented aiming silicon transistor (HBT, MOSFET) MilliMeter Wave (MMW) noise parameters (NFmin, Rn, ¿opt) extraction through multi-impedance method. This Tuner is directly integrated in On-wafer tested transistor test structure. Design, electrical simulation and MMW measurement of the Tuner are described showing capability from 60GHz up to 110GHz for CMOS and BiCMOS sub 65nm technologies characterization. ¿ of 0.88 have been achieved at the DUT input in the considered frequency range and Tuner insertion losses are less than 20 dB.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134015863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Mapping the Edge Roughness of Test-Structure Features for Nanometer-Level CD Reference-Materials 纳米级CD基准材料测试结构特征边缘粗糙度的映射
2009 IEEE International Conference on Microelectronic Test Structures Pub Date : 2009-04-14 DOI: 10.1109/ICMTS.2009.4814633
M. Cresswell, M. Davidson, G. Mijares, R. Allen, J. Geist, M. Bishop
{"title":"Mapping the Edge Roughness of Test-Structure Features for Nanometer-Level CD Reference-Materials","authors":"M. Cresswell, M. Davidson, G. Mijares, R. Allen, J. Geist, M. Bishop","doi":"10.1109/ICMTS.2009.4814633","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814633","url":null,"abstract":"The near-term objective of the work reported here is to develop a protocol for rapidly mapping CD and edge roughness from high-resolution SEM images of reference-material features patterned on Single-Crystal CD Reference Material (SCCDRM) chips. The longer term mission is to formulate a metric to enable automated characterization of as-fabricated reference-feature segments for rapid identification of fabrication-process enhancements and, ultimately, to select feature segments for further characterization as standard reference-materials. The selection of results presented here provides a new level of SCCDRM characterization which shows that segments of some SCCDRM features appear to have very useful extended lengths of up to 200 nm of superior CD uniformity.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125236298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An enhanced model for thin film resistor matching 薄膜电阻匹配的改进模型
2009 IEEE International Conference on Microelectronic Test Structures Pub Date : 2009-04-14 DOI: 10.1109/ICMTS.2009.4814608
T. O'Dwyer, Michael Peter Kennedy
{"title":"An enhanced model for thin film resistor matching","authors":"T. O'Dwyer, Michael Peter Kennedy","doi":"10.1109/ICMTS.2009.4814608","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814608","url":null,"abstract":"This paper presents an improved model which estimates the geometry required to achieve a desired matching target for rectangular resistors in a semiconductor process. A methodology is explained for estimating the model parameters involved. Measured data is presented which covers an extensive range of geometries on a particular thin film process, and the estimation methodology is followed to derive appropriate model parameters. Using this new model, insights into the underlying error sources for the process are obtained.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127434379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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