G. Steinbrueck, J. Vickers, M. Babazadeh, M. Pelella, N. Pakdaman
{"title":"Non-Contact, Pad-less Measurement Technology and Test Structures for Characterization of Cross-Wafer and In-Die Product Variability","authors":"G. Steinbrueck, J. Vickers, M. Babazadeh, M. Pelella, N. Pakdaman","doi":"10.1109/ICMTS.2009.4814617","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814617","url":null,"abstract":"Monitoring and controlling cross-wafer and in-die variability has been recognized as the dominant and escalating factors for the successful commercialization of modern-day integrated circuit products utilizing advanced semiconductor manufacturing[1,2]. In this paper we present a Performance Based Metrology (PBM), a measurement technology for closing the information gap between the design, process integration, and manufacturing groups with respect to accounting for variability. PBM enables the \"porting\" of scribe-like and end-of-line contact tested measurements to within the product die active area to it provide the capability to significantly reduce the cycles of learning to obtain relevant and key process, device, and product metrics. This product-relevant information can then be used for process monitoring and control, performance optimization, and to enhance early bin-yield predictability. The technique would reduce or eliminate the need for send-ahead test wafers and other \"disruptive\" measurements by making possible in-die, non-contact characterization of product performance monitors and devices. We describe the in-line measurement system and review the design and implementation considerations for the non-contact test structures incorporated on product wafers. Experimental results from PBM measurements on several generations (90, 65, and 45nm) of bulk-Si and SOI product wafers and devices are presented to illustrate the capabilities of the technique.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"358 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122733091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. M. Hafkemeyer, A. Domdey, D. Schroeder, W. Krautschneider
{"title":"Array Test Structure for Ultra-Thin Gate Oxide Degradation Issues","authors":"K. M. Hafkemeyer, A. Domdey, D. Schroeder, W. Krautschneider","doi":"10.1109/ICMTS.2009.4814616","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814616","url":null,"abstract":"An array test structure for highly parallelized measurements of ultra-thin MOS gate oxide failures caused by degradation is presented. The test structure allows for voltage stress tests of several thousand NMOS devices under test (DUTs) in parallel to provide a large and significant statistical base regarding soft as well as hard breakdown and stress induced degradation of transistor parameters. The array has been fabricated in a standard 130 nm CMOS technology. As mixed mode technologies provide both thin and thick oxide MOS transistors, different gate oxide thicknesses have been chosen for DUTs and digital control logic which gives the possibility to stress the DUTs with high gate voltages.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131361057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Saxena, T. Uezono, R. Vallishayee, R. Lindley, A. Swimmer, S. Winters
{"title":"Estimating MOSFET Leakage from Low-cost, Low-resolution Fast Parametric Test","authors":"S. Saxena, T. Uezono, R. Vallishayee, R. Lindley, A. Swimmer, S. Winters","doi":"10.1109/ICMTS.2009.4814623","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814623","url":null,"abstract":"A method of estimating the subthershold component of MOSFET off-state current (Ioffs) using low-cost, low-resolution fast parallel parametric test is introduced. This method measures the subthreshold slope and uses it to estimate Ioffs. Measurements of individual transistors show a very good agreement between measured Ioffs and Ioffs estimated using our approach. For a simple pad-efficient transistor array test-structure, where unselected devices can add additional noise to the subthreshold measurements, the sum of extracted Ioffs for all transistors in an array is strongly correlated to the measured array Ioffs, even though it does not match the measured array Ioffs. The strong correlation is used to derive calibration factors which are then used to estimate individual transistor Ioffs from array test structures. This allows statistical characterization of transistor leakage during volume production with minimal test time overhead. The applications of statistical off-state leakage characterization to diagnose IDDQ yield problems during production are also described.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124591746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High precision on-wafer backend capacitor mismatch measurements using a benchtop semiconductor characterization system","authors":"H. Tuinhout, F. van Rossem, N. Wils","doi":"10.1109/ICMTS.2009.4814598","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814598","url":null,"abstract":"This paper discusses a sophisticated backend capacitor mismatch characterization technique based on direct capacitance measurements with a standard C-V meter, wafer prober subsite moves to measure the two capacitors of each pair sequentially and monitor the measurement noise, and statistics to take this noise appropriately into account. We describe requirements, capabilities and limitations of this approach. It is concluded that this technique proves excellently suited for assessing the matching performance of backend capacitors in the most relevant range of 10 fF to 10 pF.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115134079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Madriz, J. Jameson, S. Krishnan, Xuhui Sun, Cary Y. Yang
{"title":"Test Structure to Extract Circuit Models of Nanostructures Operating at High Frequencies","authors":"F. Madriz, J. Jameson, S. Krishnan, Xuhui Sun, Cary Y. Yang","doi":"10.1109/ICMTS.2009.4814605","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814605","url":null,"abstract":"We describe a test structure optimized for studying high-frequency electrical transport in 1-D nanoscale systems. The test structure exhibits lower transmission than previously reported structures, enabling capacitances less than 1 fF to be detected in the frequency response of the nanoscale system. The scattering parameters (S-parameters) of the test structure are describable to within ±0.5dB and ±2° from 0.1 to 50 GHz using a simple lumped-element RC circuit model whose elements are all measured experimentally.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115605177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Watabe, S. Sugawa, K. Abe, T. Fujisawa, N. Miyamoto, A. Teramoto, T. Ohmi
{"title":"A Test Structure for Statistical Evaluation of Characteristics Variability in a Very Large Number of MOSFETs","authors":"S. Watabe, S. Sugawa, K. Abe, T. Fujisawa, N. Miyamoto, A. Teramoto, T. Ohmi","doi":"10.1109/ICMTS.2009.4814622","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814622","url":null,"abstract":"We have proposed and developed a test structure for evaluating electrical characteristics variability of a large number of MOSFETs in very short time using very simple circuit structure. The electrical characteristics such as threshold voltage, subthreshold swings (S-factors, random telegraph signal noise, and so on, can be measured in over one million MOSFETs. This new test structure circuit and results measured by this circuit are very efficient in developing processes, process equipment and device structure which suppress variability.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131599925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Amakawa, K. Yamanaga, H. Ito, T. Sato, N. Ishihara, K. Masu
{"title":"S-Parameter-Based Modal Decomposition of Multiconductor Transmission Lines and Its Application to De-Embedding","authors":"S. Amakawa, K. Yamanaga, H. Ito, T. Sato, N. Ishihara, K. Masu","doi":"10.1109/ICMTS.2009.4814635","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814635","url":null,"abstract":"Theory and experiments are presented of modal decomposition of scattering matrices of multiconductor transmission lines (TLs). In effect, n coupled TLs are decomposed into n independent ones. Its use is demonstrated by applying it to thru-only de-embedding of 4 coupled TLs (synthesized data) and 2 coupled TLs (measurement data from a 0.18 ¿m-CMOS chip). The proposed de-embedding method could greatly facilitate accurate characterization of on-chip multiport networks.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130368106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Rigaud, J. Portal, P. Dreux, J. Vast, H. Aziza, G. Baş
{"title":"Fast Embedded Characterization of FEOL Variations in MOS Devices","authors":"F. Rigaud, J. Portal, P. Dreux, J. Vast, H. Aziza, G. Baş","doi":"10.1109/ICMTS.2009.4814642","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814642","url":null,"abstract":"The objective of this paper is to present a test chip based on embedded Ring Oscillators (RO) measurement with its associated extraction algorithm to characterize length and width variations and to discriminate them from others FEOL variations. A brief overview of the structure, designed in a ST-Microelectronics 90nm technology, is given with emphasis on the ROs geometry with their biasing conditions and the measurement circuit. Comparison of simulated values versus estimated ones is given and confirms the ability of the structure to characterize FEOL variations. MOS width and length are well estimated regardless the others FEOL deviations that can be also detected.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129914228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Characterization and modeling of mechanical stress in silicon-based devices","authors":"A. Spessot, A. Colombi, G. Carnevale, P. Fantini","doi":"10.1109/ICMTS.2009.4814628","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814628","url":null,"abstract":"In this paper we show a self-consistent methodology to characterize the stress-induced mobility variation in silicon-based devices. The synergy among different experimental techniques (the application of an external mechanical stress and the measure of the process-induced stress), theoretical calculations (based on the finite elements method and the band structure calculation), and silicon validation (given by particular sets of test structures) is the strength of the characterization tool we propose.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134624856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Characterization and Model Parameter Extraction of Symmetrical Centre Tapped Inductor using Build in Mixed Mode and Pure Differential S-Parameters","authors":"F. Gianesello, Y. Morandini, S. Boret, D. Gloria","doi":"10.1109/ICMTS.2009.4814636","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814636","url":null,"abstract":"With the continuous reduction of the gate length, the cut off frequency of the active devices in CMOS technology has exceeded 200 GHz [1]. In addition, CMOS possesses the capability to integrate transceiver with the baseband circuits. Thus, CMOS technology seems to be an attractive candidate for low-gigahertz (5 GHz) radio frequency (RF) applications [2] and even millimetre wave one [3]. Then, monolithic inductors have become an important component in highly integrated radio frequency circuits (RF ICs) for wireless communication systems such as personal communication services, wireless local area networks, satellite communications, and the global positioning system. It is well known that exciting a spiral inductor differentially, using a source connected between the two ends of the inductor, the peak Q-factor shows a significant increase, and this high Q value is maintained over a broader bandwidth [4] compared to single-ended excitation. Up to now, differential characterization of symmetrical inductor has been performed using classical single ended S-parameters [5], and assuming linearity and electrical symmetry hypothesis, mixed mode Sparameters are then computed and differential quality factor extracted. In this paper, for the first time using recently available vector network analyzer capable of delivering true differential signal, PNA-X from Agilent, we will verify this hypothesis discussing dedicated differential test structure and methodology. Moreover, from the modelling side new perspective will be proposed in order to take advantage of mixed mode S-parameters to extract new parameter such as self mutual inductance.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114434960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}