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2009 IEEE International Conference on Microelectronic Test Structures最新文献

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Efficient Characterization Methodology of Gate-Bulk Leakage and Capacitance for Ultra-Thin Oxide Partially-Depleted (PD) SOI Floating Body CMOS 超薄氧化部分耗尽(PD) SOI浮体CMOS栅极体泄漏和电容的高效表征方法
2009 IEEE International Conference on Microelectronic Test Structures Pub Date : 2009-04-14 DOI: 10.1109/ICMTS.2009.4814626
David Chen, Ryan Lee, Y. C. Liu, G. Lin, Mao-Chyuan Tang, Meng Fan Wang, C. Yeh, S. Chien
{"title":"Efficient Characterization Methodology of Gate-Bulk Leakage and Capacitance for Ultra-Thin Oxide Partially-Depleted (PD) SOI Floating Body CMOS","authors":"David Chen, Ryan Lee, Y. C. Liu, G. Lin, Mao-Chyuan Tang, Meng Fan Wang, C. Yeh, S. Chien","doi":"10.1109/ICMTS.2009.4814626","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814626","url":null,"abstract":"For the first time, an efficient methodology to accurately characterize the gate-bulk leakage current (Igb) and gate capacitance (Cgg) of PD SOI floating body (FB) devices was proposed and demonstrated in 40-nm PD SOI devices with ultra-thin oxide EOT 12A. By applying the RF testing skill for the proposed SOI test patterns, we can eliminate properly the parasitic elements due to the co-existence opposite poly gate type the SOI T-shape body-tied (BT) device and accurately characterize and model the SOI FB Igb and Cgg behaviors. Impact on the history effect was analyzed by BSIMSOI4.0 model. History effect analysis with high pulse and low pulse width was shown. Improvement of more than 3% simulation accuracy for history effect was also demonstrated.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124001161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Test Structure for Assessing Individual Contact Resistance 一种评估单个接触电阻的测试结构
2009 IEEE International Conference on Microelectronic Test Structures Pub Date : 2009-04-14 DOI: 10.1109/ICMTS.2009.4814641
F. Liu, K. Agarwal
{"title":"A Test Structure for Assessing Individual Contact Resistance","authors":"F. Liu, K. Agarwal","doi":"10.1109/ICMTS.2009.4814641","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814641","url":null,"abstract":"Accurate measurement of contact resistance is crucial for advanced nanometer CMOS processes. An equally important requirement is to measure contact resistances in the same micro-environment as the device-under-test (DUT) will be used in real designs. With complicated interactions among various layout shapes in nanometer CMOS processes, test structures with adequate scalability is needed. In this paper we present a scalable contact resistance measurement structure, which can accommodate tens of thousands of DUTs. The measurement results from a 65 nm CMOS technology are also presented.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122636325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Metal and Dielectric Thickness: a Comprehensive Methodology for Back-End Electrical Characterization 金属和介电厚度:后端电特性的综合方法
2009 IEEE International Conference on Microelectronic Test Structures Pub Date : 2009-04-14 DOI: 10.1109/ICMTS.2009.4814640
L. Bortesi, L. Vendrame
{"title":"Metal and Dielectric Thickness: a Comprehensive Methodology for Back-End Electrical Characterization","authors":"L. Bortesi, L. Vendrame","doi":"10.1109/ICMTS.2009.4814640","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814640","url":null,"abstract":"Back-End-Of-Line (BEOL) process variation is becoming more and more important since technology is scaling down and increases its complexity. On-chip capacitances and resistances are strongly dependent on the BEOL geometrical configuration so it is really important to have an accurate characterization of the metal and dielectric thickness. Interconnect parasitic modelling by means of LPE tool (Layout Parasitic Extraction) or semi-analytic approximation can't neglect the impact of metal (dielectric) thickness variations. The focus of this work is to provide an accurate, simple and suitable for parametric testing methodology to electrically measure metal (dielectric) thickness, mandatory for a useful characterization and control of a technology.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"271 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116250232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Accurate Time Constant of Random Telegraph Signal Extracted by a Sufficient Long Time Measurement in Very Large-Scale Array TEG 超大规模阵列TEG中充分长时间测量提取随机电报信号的精确时间常数
2009 IEEE International Conference on Microelectronic Test Structures Pub Date : 2009-04-14 DOI: 10.1109/ICMTS.2009.4814601
T. Fujisawa, K. Abe, S. Watabe, N. Miyamoto, A. Teramoto, S. Sugawa, T. Ohmi
{"title":"Accurate Time Constant of Random Telegraph Signal Extracted by a Sufficient Long Time Measurement in Very Large-Scale Array TEG","authors":"T. Fujisawa, K. Abe, S. Watabe, N. Miyamoto, A. Teramoto, S. Sugawa, T. Ohmi","doi":"10.1109/ICMTS.2009.4814601","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814601","url":null,"abstract":"To suppress Random Telegraph Signal (RTS) noise in MOSFETs, it is necessary to understand the phenomena of RTS. We can extract the accurate time constant in RTS noise by measuring a huge number of MOSFETs during a long time. Time constant is useful to obtain the energy level. In this paper, we demonstrated the statistical and accurate measurement method of the time constant of RTS by a sufficient long measuring in very large-scale array TEG.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"209 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121546041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
An Analysis of Temperature Impact on MOSFET Mismatch 温度对MOSFET失配的影响分析
2009 IEEE International Conference on Microelectronic Test Structures Pub Date : 2009-04-14 DOI: 10.1109/ICMTS.2009.4814610
S. Mennillo, Alessio Spessot, L. Vendrame, L. Bortesi
{"title":"An Analysis of Temperature Impact on MOSFET Mismatch","authors":"S. Mennillo, Alessio Spessot, L. Vendrame, L. Bortesi","doi":"10.1109/ICMTS.2009.4814610","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814610","url":null,"abstract":"Summarizing the results collected on several technologies, we have studied the impact of temperature on MOSFET mismatch, highlighting the improvement of current gain matching properties with temperature, suggesting a possible physical explanation to this phenomenon and proposing a BSIM3 model implementation for Monte Carlo mismatch simulations.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132773584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Parameter extraction for the PSP MOSFET model by the combination of genetic and Levenberg-Marquardt algorithms 结合遗传算法和Levenberg-Marquardt算法对PSP MOSFET模型进行参数提取
2009 IEEE International Conference on Microelectronic Test Structures Pub Date : 2009-04-14 DOI: 10.1109/ICMTS.2009.4814627
Q. Zhou, W. Yao, W. Wu, Xin Li, Z. Zhu, Gennady Gildenblat
{"title":"Parameter extraction for the PSP MOSFET model by the combination of genetic and Levenberg-Marquardt algorithms","authors":"Q. Zhou, W. Yao, W. Wu, Xin Li, Z. Zhu, Gennady Gildenblat","doi":"10.1109/ICMTS.2009.4814627","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814627","url":null,"abstract":"Based on the combination of the genetic and Levenberg-Marquardt algorithms, a new method is developed to perform both local and global parameter extraction for the PSP MOSFET model. It has been successfully used to extract parameter sets for a 65-nm technology node. Numerical examples demonstrate its ability to obtain highly accurate model parameter values without excessive computational cost.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123612896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Practical Considerations for Measurements of Test Structures for Dielectric Characterization 介电特性测试结构测量的实际考虑
2009 IEEE International Conference on Microelectronic Test Structures Pub Date : 2009-04-14 DOI: 10.1109/ICMTS.2009.4814646
Wenbin Chen, K. McCarthy, A. Mathewson
{"title":"Practical Considerations for Measurements of Test Structures for Dielectric Characterization","authors":"Wenbin Chen, K. McCarthy, A. Mathewson","doi":"10.1109/ICMTS.2009.4814646","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814646","url":null,"abstract":"This paper presents a method for measuring the complex permittivity of dielectric material on a dielectric/metal stack. A series of circular capacitor and transmission line test structures are designed and fabricated. The methodology has been verified by measuring the dielectric constant of a known SiO2 layer using Capacitance-Voltage (C-V) measurement and scattering parameter (S-parameter) measurements. The combination of C-V measurement and S-parameter measurement is shown to be suitable for characterization of dielectric material on the complex cross-sections.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125360882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Automated Test Structure Generation for Characterizing Plasma Induced Damage in MOSFET D vices 用于表征MOSFET D器件等离子体诱导损伤的自动化测试结构生成
2009 IEEE International Conference on Microelectronic Test Structures Pub Date : 2009-04-14 DOI: 10.1109/ICMTS.2009.4814619
Thomas Zwingman, A. Gabrys, A.J. West
{"title":"Automated Test Structure Generation for Characterizing Plasma Induced Damage in MOSFET D vices","authors":"Thomas Zwingman, A. Gabrys, A.J. West","doi":"10.1109/ICMTS.2009.4814619","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814619","url":null,"abstract":"Test structures used to study the effects of plasma induced damage are complex and time intensive to design; performance problems due to poorly designed components of the structure often confound the desired result. This paper presents a parameterized and hierarchical antenna test structure template that enables the user to characterize the test structure performance and identify safe design guidelines early in process development. The template is implemented in a system that automates structure generation, placement, routing, and test plan development.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132677216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Improved Parameter Extraction Procedure for PSP-Based MOS Varactor Model 基于psp的MOS变容管模型参数提取方法的改进
2009 IEEE International Conference on Microelectronic Test Structures Pub Date : 2009-04-14 DOI: 10.1109/ICMTS.2009.4814629
Z. Zhu, J. Victory, S. Chaudhry, L. Dong, Z. Yan, J. Zheng, W. Wu, X. Li, Q. Zhou, P. Kolev, C. McAndrew, G. Gildenblat
{"title":"Improved Parameter Extraction Procedure for PSP-Based MOS Varactor Model","authors":"Z. Zhu, J. Victory, S. Chaudhry, L. Dong, Z. Yan, J. Zheng, W. Wu, X. Li, Q. Zhou, P. Kolev, C. McAndrew, G. Gildenblat","doi":"10.1109/ICMTS.2009.4814629","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814629","url":null,"abstract":"We present an improved procedure for extracting parasitic capacitance parameters and gate current parameters for MOSVAR, the industry standard MOS varactormodel. Our technique is verified against measured data from three technology nodes (180 nm, 130 nm and 65 nm), and is also used to validate the MOSVAR P-gate/P-well tunneling current sub-model.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133851318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Four point probe structures with buried electrodes for the electrical characterization of ultrathin conducting films 用于超薄导电膜电学表征的埋电极四点探针结构
2009 IEEE International Conference on Microelectronic Test Structures Pub Date : 2009-04-14 DOI: 10.1109/ICMTS.2009.4814639
A. Groenland, R. Wolters, A. Kovalgin, Jurriaan Schmitz
{"title":"Four point probe structures with buried electrodes for the electrical characterization of ultrathin conducting films","authors":"A. Groenland, R. Wolters, A. Kovalgin, Jurriaan Schmitz","doi":"10.1109/ICMTS.2009.4814639","DOIUrl":"https://doi.org/10.1109/ICMTS.2009.4814639","url":null,"abstract":"Test structures for the electrical characterization of ultrathin conductive (ALD) films are presented based on buried electrodes on which the ultrathin film is deposited. This work includes test structure design and fabrication, and the electrical characterization of ALD TiN films down to 4 nm. It is shown that these structures can be used successfully to characterize sub 10 nm films.","PeriodicalId":175818,"journal":{"name":"2009 IEEE International Conference on Microelectronic Test Structures","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114958731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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