J. Ryan, R. Southwick, J. Campbell, K. Cheung, J. Suehle
{"title":"Frequency dependent charge pumping — A defect depth profiling tool?","authors":"J. Ryan, R. Southwick, J. Campbell, K. Cheung, J. Suehle","doi":"10.1109/IIRW.2012.6468942","DOIUrl":"https://doi.org/10.1109/IIRW.2012.6468942","url":null,"abstract":"We investigate the validity of using frequency-dependent charge pumping (FD-CP) to determine bulk defect depth distributions. Using simple physical arguments we conclude that: (1) the effective tunneling length to a bulk defect can be very different than its actual physical depth, and (2) only a fraction of detrapping charge may contribute to the CP current (ICP) resulting in analysis errors. Thus, the relationship between frequency and defect depth is much more complex than what has been previously reported.","PeriodicalId":165120,"journal":{"name":"2012 IEEE International Integrated Reliability Workshop Final Report","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126968438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modeling of hot-carrier degradation: Physics and controversial issues","authors":"S. Tyaginov, T. Grasser","doi":"10.1109/IIRW.2012.6468962","DOIUrl":"https://doi.org/10.1109/IIRW.2012.6468962","url":null,"abstract":"We discuss and analyze the main features of hot-carrier degradation (HCD) which are a strong localization at the drain-side of the device, the interplay between single- and multiple-particle processes of Si-H bond dissociation, the transition of the worst-case scenario when going from long- to short-channel devices, and its temperature dependence. These main peculiarities are then linked to the physical processes responsible for HCD. We show that the problem can be conditionally separated into three main subtasks: the carrier transport aspect, the kinetics of defect generation, and modeling of the degraded devices. From this perspective, the most important physics-based models and their validity are discussed. In order to obtain a most accurate description of HCD, we try to minimize the number of empirical parameters by basing our own model on a thorough treatment of carrier transport. Finally, we discuss one of the most important open obstacles towards the understanding of HCD, namely whether bulk oxide traps contribute to the damage or not.","PeriodicalId":165120,"journal":{"name":"2012 IEEE International Integrated Reliability Workshop Final Report","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128974249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Sagong, C. Kang, C. Sohn, E. Jeong, D. Choi, S. Lee, Y. Kim, J. Jang, Y. Jeong
{"title":"An experimental study on channel backscattering in high-k/metal gate nMOSFETs","authors":"H. Sagong, C. Kang, C. Sohn, E. Jeong, D. Choi, S. Lee, Y. Kim, J. Jang, Y. Jeong","doi":"10.1109/IIRW.2012.6468948","DOIUrl":"https://doi.org/10.1109/IIRW.2012.6468948","url":null,"abstract":"Quasi-ballistic transport in nanoscale high-k/metal gate nMOSFETs is investigated by RF S-parameter analysis. A simple experimental method based on RF S-parameter is used for direct extraction of device parameters (Leff, Cgc, RSD) and the effective carrier velocity (veff) from targeted short channel devices. The ballistic carrier velocity (vinj) at the top of the barrier near the source is determined by using the top-of-the-barrier model which self-consistently solves Schrödinger-Poisson equations. Combining the experimental extraction and the analytical top-of-the-barrier model, the backscattering coefficient (rsat) is calculated to assess the degree of the transport ballisticity for the high-k/metal gate nMOSFETs.","PeriodicalId":165120,"journal":{"name":"2012 IEEE International Integrated Reliability Workshop Final Report","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130455537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Angot, D. Rideau, A. Bravaix, F. Monsieur, Y. M. Randriamihaja, V. Huard
{"title":"New insights into NBTI reliability in UTBOX-FDSOI PMOS transistors","authors":"D. Angot, D. Rideau, A. Bravaix, F. Monsieur, Y. M. Randriamihaja, V. Huard","doi":"10.1109/IIRW.2012.6468923","DOIUrl":"https://doi.org/10.1109/IIRW.2012.6468923","url":null,"abstract":"Based on capacitive measurements combined with TCAD simulations, in a wide range of bulk biases, the impact of NBTI on both oxide-silicon interfaces of FDSOI transistors is evaluated. Physical modeling is proposed to fully analyze the degradation mechanisms and reproduce the experimental behaviors through the help of accurate simulations of the back bias dependence in the FDSOI structure.","PeriodicalId":165120,"journal":{"name":"2012 IEEE International Integrated Reliability Workshop Final Report","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131004381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Effect of temperature and exposure to moisture on leakage through VDP liners in TSV structures","authors":"S. W. Fall, J. Lloyd","doi":"10.1109/IIRW.2012.6468944","DOIUrl":"https://doi.org/10.1109/IIRW.2012.6468944","url":null,"abstract":"Bake recoverable leakage in TSV (Through Silicon Via) structures was studied as a function of annealing and exposure to damp heat. It was demonstrated, unexpectedly, that moisture was not the source of the leakage as had been observed previously in integrated circuits. The data generated here suggests a new phenomenon not related to absorbed moisture. The test data, while not determining a cause, shows no correlation (in the VDP material tested) between an initial bump in leakage current and chemisorbed moisture. Despite that, a link between a bump in initial leakage current and an unknown vector (possibly an absorbed solvent other than water) was in fact found.","PeriodicalId":165120,"journal":{"name":"2012 IEEE International Integrated Reliability Workshop Final Report","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131193916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Ighilahriz, F. Cacho, V. Huard, L. Moquillon, P. Benech, J. Fournier
{"title":"HBT reliability modeling strategy for BICMOS RF and mmW applications","authors":"S. Ighilahriz, F. Cacho, V. Huard, L. Moquillon, P. Benech, J. Fournier","doi":"10.1109/IIRW.2012.6468931","DOIUrl":"https://doi.org/10.1109/IIRW.2012.6468931","url":null,"abstract":"Heterojunction bipolar transistors, SiGe, Reliability, DC and AC stress, Dynamic parameters, Low frequency noise, Mixer, Voltage controlled oscillator, Low noise amplifier, RF stress, SOA.","PeriodicalId":165120,"journal":{"name":"2012 IEEE International Integrated Reliability Workshop Final Report","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132824263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On the impact of the layout of MOSFET test-structures on NBTI-, PBTI- and HCS-lifetime due to PID","authors":"C. Schlunder, A. Martin","doi":"10.1109/IIRW.2012.6468926","DOIUrl":"https://doi.org/10.1109/IIRW.2012.6468926","url":null,"abstract":"We introduce and discuss in our paper an alternative to protection diodes and compare it with different sizes and placements of diodes. In contrast to other PID publications we do not focus on the PID itself but on the impact on full transistor-lifetime estimations. We evaluate long-term NBTI, PBTI and HCS experiments.","PeriodicalId":165120,"journal":{"name":"2012 IEEE International Integrated Reliability Workshop Final Report","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114519334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Lim, J. Jimenez, P. Benech, J. Fournier, B. Heitz, P. Galy
{"title":"Geometrical impact on RF performances of broadband ESD self protected transmission line in advanced CMOS technologies","authors":"T. Lim, J. Jimenez, P. Benech, J. Fournier, B. Heitz, P. Galy","doi":"10.1109/IIRW.2012.6468951","DOIUrl":"https://doi.org/10.1109/IIRW.2012.6468951","url":null,"abstract":"Advanced CMOS technologies provide an easy way to realize radio-frequency integrated circuits (RFICs). However, transistor gates are getting smaller and electrostatic discharge (ESD) issues become more significant. Unfortunately, parasitic capacitance of the ESD protection limits the operating bandwidth of the RFICs. The size (i.e. die area) of ESD protection is also of concern in RFICs. This paper presents results of transmission line with ESD protection devices able to be implemented in an I/O pad in advanced CMOS technologies.","PeriodicalId":165120,"journal":{"name":"2012 IEEE International Integrated Reliability Workshop Final Report","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125052037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Chery, X. Federspiel, G. Beylier, F. Volpi, J. Chaix
{"title":"A method for low-K dielectric breakdown physical localization","authors":"E. Chery, X. Federspiel, G. Beylier, F. Volpi, J. Chaix","doi":"10.1109/IIRW.2012.6468934","DOIUrl":"https://doi.org/10.1109/IIRW.2012.6468934","url":null,"abstract":"This paper reports results obtained on a new test structure developed to easily locate low-k dielectric breakdown spots. This spot can be localized by using a comb-serpentine test structure, and by monitoring the change in resistance between pads.","PeriodicalId":165120,"journal":{"name":"2012 IEEE International Integrated Reliability Workshop Final Report","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122200791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Frank, E. Chery, C. Chappaz, L. Arnaud, L. Anghel
{"title":"Through silicon via impact on above BEoL Time Dependent Dielectric Breakdown","authors":"T. Frank, E. Chery, C. Chappaz, L. Arnaud, L. Anghel","doi":"10.1109/IIRW.2012.6468916","DOIUrl":"https://doi.org/10.1109/IIRW.2012.6468916","url":null,"abstract":"The impact of Through Silicon Via (TSV) on above BEoL dielectric reliability is studied. Time Dependent Dielectric Breakdown (TDDB) is performed on copper dual damascene combs, fabricated in a 65 nm technology node with a SiOCH low-k dielectric, and designed above 10μm diameter and 80μm thick TSVs, processed through a via-middle approach.","PeriodicalId":165120,"journal":{"name":"2012 IEEE International Integrated Reliability Workshop Final Report","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131528126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}