2012 IEEE International Integrated Reliability Workshop Final Report最新文献_第3页

Improved reliability of rarely switching CMOS circuits in ULSI devices 提高了ULSI器件中很少开关的CMOS电路的可靠性

2012 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2012-10-01 DOI: 10.1109/IIRW.2012.6468950

S. Sofer, P. Livshits, M. Priel

引用次数: 1

A means to study reliability based defects in fully processed devices utilizing zero-field spin dependent transport 一种利用零场自旋相关输运研究全加工器件可靠性缺陷的方法

2012 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2012-10-01 DOI: 10.1109/IIRW.2012.6468917

C. Cochrane, P. Lenahan

{"title":"A means to study reliability based defects in fully processed devices utilizing zero-field spin dependent transport","authors":"C. Cochrane, P. Lenahan","doi":"10.1109/IIRW.2012.6468917","DOIUrl":"https://doi.org/10.1109/IIRW.2012.6468917","url":null,"abstract":"Electron paramagnetic resonance (EPR) and electrically detected magnetic resonance (EDMR) are extremely useful techniques that are capable of defect detection in semiconductor structures and fully processed devices, respectively. The complexity of conventional EPR and EDMR spectrometers involves utilization of strong (>3000 G) highly uniform magnetic fields (B0) and high frequency (typically 9 GHz) oscillating magnetic fields (B1) or higher. These components are typically expensive and heavy. In this study, we directly demonstrate that, in the absence of both an oscillating magnetic field and a large static magnetic field, spin dependent recombination (SDR) and spin dependent tunneling (SDT) can be detected at zero magnetic field. In this zero-field detection scheme, hyperfine interactions can be detected which allow for the physical identification of the defects responsible for SDR and SDT. However, we sacrifice the evaluation of a resonance parameter, the g-value. We observe the zero-field phenomenon in multiple solid state electronic components including MOSFETs, BJTs, diodes, and capacitors suggesting its usefulness for semiconducting manufacturers to incorporate simple automated low-field/zero-field EDMR spectrometers into wafer fabrication/probing equipment to study the defects in solid-state electronics during fabrication. Because only very low fields are required, low field EDMR can be performed easily and inexpensively.","PeriodicalId":165120,"journal":{"name":"2012 IEEE International Integrated Reliability Workshop Final Report","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121553293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Degradation of GaN high-electron mobility transistors in voltage step stress 电压阶跃应力下氮化镓高电子迁移率晶体管的退化

2012 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2012-10-01 DOI: 10.1109/IIRW.2012.6468935

Xinhua Wang, L. Pang, Jianhui Wang, T. Yuan, W. Luo, Xiaojuan Chen, Xinyu Liu

引用次数: 4

Characterization of cell to cell interference in TANOS NAND flash memory TANOS NAND快闪记忆体中细胞间干扰的表征

2012 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2012-10-01 DOI: 10.1109/IIRW.2012.6468918

Byeong-In Choe, Jong-Ho Lee

引用次数: 1

Solder Joint Reliability: An integrated study of Electromigration, Thermal Migration and thermo-mechanical effects 焊点可靠性:电迁移、热迁移和热机械效应的综合研究

2012 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2012-10-01 DOI: 10.1109/IIRW.2012.6468936

M. Forde, K. Manning, S. Kudtarkar

引用次数: 1

On-the-fly extraction method for interface-, oxide- trap and mobility degradation induced by NBTI stress NBTI应力引起的界面、氧化陷阱和迁移率退化的动态提取方法

2012 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2012-10-01 DOI: 10.1109/IIRW.2012.6468932

H. Tahi, B. Djezzar, A. Benabedelmoumene, A. Chenouf

引用次数: 4

A generalized time-series data format for efficient exchange, archiving, and analysis of reliability data 一种用于有效交换、存档和分析可靠性数据的通用时间序列数据格式

2012 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2012-10-01 DOI: 10.1109/IIRW.2012.6468946

T. Kopley, T. Dungan

引用次数: 0

The application of a modified Blech product to aluminum-based metallization for increased current density 改性Blech产品在铝基金属化中的应用，以提高电流密度

2012 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2012-10-01 DOI: 10.1109/IIRW.2012.6468937

K. Manning

引用次数: 1

Does PMOS Vth shift wholly capture the degradation of CMOS inverter circuit under DC NBTI? PMOS五阶位移是否完全反映了直流NBTI作用下CMOS逆变电路的退化?

2012 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2012-10-01 DOI: 10.1109/IIRW.2012.6468953

A. Chenouf, B. Djezzar, A. Benabedelmoumene, H. Tahi

{"title":"Does PMOS Vth shift wholly capture the degradation of CMOS inverter circuit under DC NBTI?","authors":"A. Chenouf, B. Djezzar, A. Benabedelmoumene, H. Tahi","doi":"10.1109/IIRW.2012.6468953","DOIUrl":"https://doi.org/10.1109/IIRW.2012.6468953","url":null,"abstract":"In this paper, an experimental investigation of negative bias temperature instability (NBTI) impact on CMOS inverter circuit is presented. The study focuses on the contribution of NBTI induced PMOS Vth shift on the degradation of the circuit DC features. This investigation was conducted in order to understand the origin of performance shifts due to NBTI at the circuit level and to properly predict the lifetime of the inverter circuit. The experimental setup was based on a measure/stress/measure procedure, where a series of negative gate voltages at different temperatures were applied via an automated test bench to the circuit under test. The results we obtained show, on one side, the CMOS inverter voltage transfer curve (VTC) shifts under NBTI stress to the left side, as predicted by the theory. This shift implies a shift of the critical logic voltages of the inverter. On the other side, the analysis of the logic threshold shift with respect to the inverter's PMOS threshold voltage shift shows clearly, and contrary to predicted by theory, that PMOS threshold voltage (Vth) shift does not wholly capture the degradation of the CMOS inverter logic threshold shift. In fact, this later is found to be affected by both PMOS and NMOS Vth shifts. Therefore, it cannot be unconditionally assumed that the effect of NBTI on CMOS circuits could be exclusively predicted by only shifting the PMOS Vth.","PeriodicalId":165120,"journal":{"name":"2012 IEEE International Integrated Reliability Workshop Final Report","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125568186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Diffusion along triple junctions is this the pathway for narrow Cu conductor lines? 沿着三联结扩散这是窄铜导体线的途径吗?

2012 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2012-10-01 DOI: 10.1109/IIRW.2012.6468943

J. Lloyd, S. Adamshick, C. Durcan, Y. Kandel, I. N. Lund, B. McGowan, C. Settens, Z. Zhang

引用次数: 0