{"title":"提高了ULSI器件中很少开关的CMOS电路的可靠性","authors":"S. Sofer, P. Livshits, M. Priel","doi":"10.1109/IIRW.2012.6468950","DOIUrl":null,"url":null,"abstract":"In this work, novel configurations of rarely switching ULSI I/O circuits, which provide a \"refresh\" operation allowing for temporal bias removal without any changes in the logic state or electrical characteristics of these circuits, are presented. This bias removal significantly reduces the aging of the circuits and allows for the lessening of design timing margins, thus reducing the overall design costs.","PeriodicalId":165120,"journal":{"name":"2012 IEEE International Integrated Reliability Workshop Final Report","volume":"62 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Improved reliability of rarely switching CMOS circuits in ULSI devices\",\"authors\":\"S. Sofer, P. Livshits, M. Priel\",\"doi\":\"10.1109/IIRW.2012.6468950\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, novel configurations of rarely switching ULSI I/O circuits, which provide a \\\"refresh\\\" operation allowing for temporal bias removal without any changes in the logic state or electrical characteristics of these circuits, are presented. This bias removal significantly reduces the aging of the circuits and allows for the lessening of design timing margins, thus reducing the overall design costs.\",\"PeriodicalId\":165120,\"journal\":{\"name\":\"2012 IEEE International Integrated Reliability Workshop Final Report\",\"volume\":\"62 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE International Integrated Reliability Workshop Final Report\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IIRW.2012.6468950\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE International Integrated Reliability Workshop Final Report","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IIRW.2012.6468950","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Improved reliability of rarely switching CMOS circuits in ULSI devices
In this work, novel configurations of rarely switching ULSI I/O circuits, which provide a "refresh" operation allowing for temporal bias removal without any changes in the logic state or electrical characteristics of these circuits, are presented. This bias removal significantly reduces the aging of the circuits and allows for the lessening of design timing margins, thus reducing the overall design costs.
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