2012 IEEE International Integrated Reliability Workshop Final Report最新文献

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Reliability investigations of down-stream copper interconnect with different Tungsten-VIA structures 不同钨- via结构的下游铜互连可靠性研究
2012 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2012-10-01 DOI: 10.1109/IIRW.2012.6468915
A. Teng, R. Tu, R. Chen, Ming-Yi Lee, A. Kuo, A. Dai, Shih-Chin Lee, T. Wen, B. Han, Chih-Yuan Lu
{"title":"Reliability investigations of down-stream copper interconnect with different Tungsten-VIA structures","authors":"A. Teng, R. Tu, R. Chen, Ming-Yi Lee, A. Kuo, A. Dai, Shih-Chin Lee, T. Wen, B. Han, Chih-Yuan Lu","doi":"10.1109/IIRW.2012.6468915","DOIUrl":"https://doi.org/10.1109/IIRW.2012.6468915","url":null,"abstract":"The reliability assessments of tungsten via to copper interconnect were investigated. Three layout schemes of full-landing, just-landing and un-landing via structure showed similar characteristics of electromigration: The activation energy is about 0.8 eV and current density exponent is about 1.9, which means the failure symptoms of interfacial diffusivity and line depletion stress. In this paper, we discussed the relations between mean-time-to-failure and line-end-extension. The lifetime of electromigration is proportional to logarithm of extended spacing, which is attributed to difference of mechanical stress by performing stress migration test. The model was provided a simple reliability assessment of via landing structure for definition of process pitch during technology development that could reduce the chip size and keep good reliability in the same time.","PeriodicalId":165120,"journal":{"name":"2012 IEEE International Integrated Reliability Workshop Final Report","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124118772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reverse bias stress test of GaN HEMTs for high-voltage switching applications 用于高压开关应用的GaN hemt的反向偏置应力测试
2012 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2012-10-01 DOI: 10.1109/IIRW.2012.6468930
M. Dammann, H. Czap, J. Ruster, M. Baeumler, F. Gutle, P. Waltereit, F. Benkhelifa, R. Reiner, M. Casar, H. Konstanzer, S. Muller, R. Quay, M. Mikulla, O. Ambacher
{"title":"Reverse bias stress test of GaN HEMTs for high-voltage switching applications","authors":"M. Dammann, H. Czap, J. Ruster, M. Baeumler, F. Gutle, P. Waltereit, F. Benkhelifa, R. Reiner, M. Casar, H. Konstanzer, S. Muller, R. Quay, M. Mikulla, O. Ambacher","doi":"10.1109/IIRW.2012.6468930","DOIUrl":"https://doi.org/10.1109/IIRW.2012.6468930","url":null,"abstract":"The degradation of packaged GaN HEMTs for high power applications has been studied under long term reverse bias step stress tests. Increases of leakage current and dynamic Ron resistance have been found. This degradation is possibly caused by the formation of localized defects which have been observed by backside electroluminescence imaging. In addition the effect of device layout and substrate material on the dynamic Ron as well as its temperature, recovery behavior, and drain voltage dependence have been investigated on wafer-level. The recovery behavior and the temperature dependence indicate that the dynamic Ron resistance increase is caused by surface or buffer carrier trapping. By reducing the buffer trap density the dynamic Ron resistance was reduced. A slightly higher dynamic Ron of GaN HEMTs on silicon compared to transistors on SiC substrate has been observed.","PeriodicalId":165120,"journal":{"name":"2012 IEEE International Integrated Reliability Workshop Final Report","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129781076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Advanced data analysis algorithms for the time-dependent defect spectroscopy of NBTI NBTI时效缺陷谱的先进数据分析算法
2012 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2012-10-01 DOI: 10.1109/IIRW.2012.6468924
M. Waltl, P. Wagner, H. Reisinger, K. Rott, T. Grasser
{"title":"Advanced data analysis algorithms for the time-dependent defect spectroscopy of NBTI","authors":"M. Waltl, P. Wagner, H. Reisinger, K. Rott, T. Grasser","doi":"10.1109/IIRW.2012.6468924","DOIUrl":"https://doi.org/10.1109/IIRW.2012.6468924","url":null,"abstract":"In order to identify the physical mechanisms behind the negative bias temperature instability (NBTI), the time-dependent defect spectroscopy (TDDS) has been recently proposed. The TDDS takes advantage of the fact that in nano-scaled devices only a handful of defects are present. As a consequence, degradation and recovery proceed in discrete steps, each of them corresponding to a charge capture or emission event. By repeatedly applying stress and recovery conditions, the TDDS analyzes the statistical properties of these discrete events. The measurement window of the TDDS is very large, but the occurrence of random telegraph noise (RTN) at certain biases/temperatures can limit its applicability. We have developed an advanced data analysis method which can also deal with data contaminated by RTN. The algorithm is based on the combination of a bootstrapping technique and cumulative sum charts. A benefit of the new method is the possibility to detect steps in a large class of different signals with a feasible amount of parameters. Moreover, de-/trapping parameters of the random telegraph noise (RTN) become accessible as well.","PeriodicalId":165120,"journal":{"name":"2012 IEEE International Integrated Reliability Workshop Final Report","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133040406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Two-point capacitance-voltage (TPCV) concept: A new method for NBTI characterization 两点电容电压(TPCV)概念:一种表征NBTI的新方法
2012 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2012-10-01 DOI: 10.1109/IIRW.2012.6468949
A. Benabdelmoumene, B. Djezzar, H. Tahi, A. Chenouf, L. Trombetta, M. Kechouane
{"title":"Two-point capacitance-voltage (TPCV) concept: A new method for NBTI characterization","authors":"A. Benabdelmoumene, B. Djezzar, H. Tahi, A. Chenouf, L. Trombetta, M. Kechouane","doi":"10.1109/IIRW.2012.6468949","DOIUrl":"https://doi.org/10.1109/IIRW.2012.6468949","url":null,"abstract":"Negative bias temperature instability (NBTI) in MOS capacitors has been investigated using a novel NBTI measurement method, named two-point capacitance-voltage (TPCV). This method is based on C-V techniques and allows one to independently separate the interface (ΔN<sub>it</sub>) and oxide traps (ΔN<sub>ot</sub>) induced by NBTI. For the first time, to our knowledge, such a method is proposed. The TPCV method permits a broad investigation in reliability studies by exploiting changes in capacitance. It is based on a simple theoretical concept and consists of measuring the evolution of capacitance at two points; the first at the flat-band voltage (V<sub>fb</sub>) and the second at V<sub>fb</sub> + ΔV. By assuming a linear CV characteristic variation between V<sub>fb</sub> and mid-gap voltage (V<sub>mg</sub>), the relations of voltage shifts components (V<sub>fb</sub>, V<sub>mg</sub>, and V<sub>it</sub>) are developed. The experimental results have shown that the proposed approach allows reducing the recovery amount compared to full CV characteristics. The trapped charge, ΔN<sub>ot</sub> and ΔN<sub>it</sub> present a power law stress-time-dependence. In addition, the results have shown a quasi different kinetic of interface state generation as well as oxide trapped charges, while the component ΔN<sub>ot</sub> is greater than ΔN<sub>it</sub>.","PeriodicalId":165120,"journal":{"name":"2012 IEEE International Integrated Reliability Workshop Final Report","volume":"91 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133204759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Small-signal and DC characterization of stressed GaN-on-Si HEMTs 应力GaN-on-Si hemt的小信号和直流表征
2012 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2012-10-01 DOI: 10.1109/IIRW.2012.6468952
M. Bloom, R. W. White, M. Porter, D. Derickson, T. Weatherford
{"title":"Small-signal and DC characterization of stressed GaN-on-Si HEMTs","authors":"M. Bloom, R. W. White, M. Porter, D. Derickson, T. Weatherford","doi":"10.1109/IIRW.2012.6468952","DOIUrl":"https://doi.org/10.1109/IIRW.2012.6468952","url":null,"abstract":"Shifts in GaN-on-Si HEMT device characteristics due to the combined effects of high electrical field stress, thermal stress, and electron trapping are reported. A stressing experiment is carried out to analyze the effects of high symmetrical electric field distributions upon device degradation for four groups of commercial GaN-on-Si devices. Characterization of degradation involved analyzing I-V characteristics, transfer characteristics, and S-parameters before and after stressing. Results from these experiments show an expected increase in gate leakage, but also return an increase in saturation drain current, a negative shift in threshold voltage, and a decrease in reverse transmission gain and associated small signal gate-to-drain capacitance after stressing under a symmetrical electric field distribution.","PeriodicalId":165120,"journal":{"name":"2012 IEEE International Integrated Reliability Workshop Final Report","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123741551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Dielectric breakdown in high-K metal gate: Measurement, device level model and application to circuit 高k金属栅极介质击穿:测量、器件级模型及在电路中的应用
2012 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2012-10-01 DOI: 10.1109/IIRW.2012.6468940
F. Cacho, D. Angot, M. Saliva, P. Mora, M. Rafik, X. Federspiel, D. Roy, V. Huard
{"title":"Dielectric breakdown in high-K metal gate: Measurement, device level model and application to circuit","authors":"F. Cacho, D. Angot, M. Saliva, P. Mora, M. Rafik, X. Federspiel, D. Roy, V. Huard","doi":"10.1109/IIRW.2012.6468940","DOIUrl":"https://doi.org/10.1109/IIRW.2012.6468940","url":null,"abstract":"Gate oxide breakdown is an important reliability issue. This mechanism is widely investigated at device level but the development of a compact model and the assessment at circuit level is much more complex to handle. We first characterize soft and hard breakdown with highlighting the different electrical signatures and sign change of the ratio source drain current. Then a transistor-level model of breakdown is presented. The model is calibrated for a large range of breakdown severity. Finally the model is used at circuit level. The impact of breakdown on both static current and frequency of ring oscillator is discussed.","PeriodicalId":165120,"journal":{"name":"2012 IEEE International Integrated Reliability Workshop Final Report","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122828324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Program disturbs and process optimization in a 65 nm Flash FPGA 65nm Flash FPGA中的程序干扰与工艺优化
2012 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2012-10-01 DOI: 10.1109/IIRW.2012.6468933
J. Jia, P. Singaraju, H. Micael, P. Liu, S. Sammie, F. Dhaoui, F. Hawley, Chi Ren, Zhi Guo Li, Boon Keat Toh, Zhao Bing Li, T. Chang, Jing Horng Gau, Y. Sheu
{"title":"Program disturbs and process optimization in a 65 nm Flash FPGA","authors":"J. Jia, P. Singaraju, H. Micael, P. Liu, S. Sammie, F. Dhaoui, F. Hawley, Chi Ren, Zhi Guo Li, Boon Keat Toh, Zhao Bing Li, T. Chang, Jing Horng Gau, Y. Sheu","doi":"10.1109/IIRW.2012.6468933","DOIUrl":"https://doi.org/10.1109/IIRW.2012.6468933","url":null,"abstract":"We present studies of an extrinsic program disturb mechanism in a Field Programmable Gate Array (FPGA) fabricated with a 65 nm embedded-Flash process. It is concluded that multiple positive charges are involved during disturb to explain the observed extrinsic behavior. Its failure rate was improved with tunnel oxidation process tuning and stronger pre-oxidation cleans.","PeriodicalId":165120,"journal":{"name":"2012 IEEE International Integrated Reliability Workshop Final Report","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132777800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Physical modeling of voltage-driven resistive switching in oxide RRAM 氧化RRAM中电压驱动电阻开关的物理建模
2012 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2012-10-01 DOI: 10.1109/IIRW.2012.6468905
D. Ielmini, S. Larentis, S. Balatti
{"title":"Physical modeling of voltage-driven resistive switching in oxide RRAM","authors":"D. Ielmini, S. Larentis, S. Balatti","doi":"10.1109/IIRW.2012.6468905","DOIUrl":"https://doi.org/10.1109/IIRW.2012.6468905","url":null,"abstract":"Resistive switching random access memory (RRAM) offers fast switching, high endurance and CMOS-compatible integration. Although functional devices below 10 nm have been already demonstrated, assessing the ultimate scaling of RRAM requires a detailed understanding and modeling of switching and reliability processes. This work discusses the modeling of bipolar switching in RRAM. An analytical model is first introduced to describe the temperature- and field-accelerated growth of the conductive filament (CF) induced by ion migration. The analytical model accounts for time-resolved data of the set transition, highlighting the central role of voltage as the driving parameter for set/reset transitions. The analytical model also accounts for the switching parameters as a function of the compliance current. A numerical model is then presented, allowing for a detailed description of the gradual increase during the reset transition. The numerical model highlights the different CF morphology in programmed states obtained by either set or reset. The improved insight into the switching process and the newly developed simulation tools enable device design, reliability prediction and materials engineering in RRAM.","PeriodicalId":165120,"journal":{"name":"2012 IEEE International Integrated Reliability Workshop Final Report","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124913997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Series resistance: A monitor for hot carrier stress 串联电阻:热载流子应力的监视器
2012 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2012-10-01 DOI: 10.1109/IIRW.2012.6468945
J. Campbell, S. Drozdov, K. Cheung, R. Southwick, J. Ryan, J. Suehle, A. Oates
{"title":"Series resistance: A monitor for hot carrier stress","authors":"J. Campbell, S. Drozdov, K. Cheung, R. Southwick, J. Ryan, J. Suehle, A. Oates","doi":"10.1109/IIRW.2012.6468945","DOIUrl":"https://doi.org/10.1109/IIRW.2012.6468945","url":null,"abstract":"In this work, we examine a series resistance extraction technique which yields accurate values from singe nano-scale devices. The series resistance values, derived from this extraction technique, are shown to be sensitive to hot carrier degradation and might possibly serve as new technique to monitor reliability in advanced devices.","PeriodicalId":165120,"journal":{"name":"2012 IEEE International Integrated Reliability Workshop Final Report","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121858823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On component reliability and system reliability for automotive applications 汽车零部件可靠性和系统可靠性
2012 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2012-10-01 DOI: 10.1109/IIRW.2012.6468947
A. Aal, T. Polte
{"title":"On component reliability and system reliability for automotive applications","authors":"A. Aal, T. Polte","doi":"10.1109/IIRW.2012.6468947","DOIUrl":"https://doi.org/10.1109/IIRW.2012.6468947","url":null,"abstract":"A new strategy is proposed for automotive system reliability design. Such strategy aims to overcome the discrepancy between single component reliability and system lifetime/performance requirements. While the design for X (DfX, X: reliability, testability, manufacturability, ...) methodology is part of every state-of-the art semiconductor development, it remains that reliability specifications and ppm goals of a products are strongly application and sector specific. It is therefore especially necessary to understand the aging behavior of system-integrated components, each of which must work beyond their foreseen lifetime targets, as well as to understand the effect of steady-state and varying failure rates on system performance. We propose to extend component failure rate assessment based on the regular useful life phase (exponential distributions) by also including early and wear out phase completely with corresponding Weibull distributions with their scale parameters dependent on competing dominant modes in these regimes. By doing so, the system design and verification cycle can be shortened and further improved, saving both time and costs.","PeriodicalId":165120,"journal":{"name":"2012 IEEE International Integrated Reliability Workshop Final Report","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122646341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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