65nm Flash FPGA中的程序干扰与工艺优化

2012 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2012-10-01 DOI:10.1109/IIRW.2012.6468933

J. Jia, P. Singaraju, H. Micael, P. Liu, S. Sammie, F. Dhaoui, F. Hawley, Chi Ren, Zhi Guo Li, Boon Keat Toh, Zhao Bing Li, T. Chang, Jing Horng Gau, Y. Sheu

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引用次数: 1

摘要

我们提出了一种外部程序干扰机制在现场可编程门阵列(FPGA)制造与65nm嵌入式闪存工艺。结论是在扰动过程中涉及到多个正电荷来解释观察到的外在行为。通过隧道氧化工艺调整和强化预氧化清洗，提高了其故障率。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Program disturbs and process optimization in a 65 nm Flash FPGA

We present studies of an extrinsic program disturb mechanism in a Field Programmable Gate Array (FPGA) fabricated with a 65 nm embedded-Flash process. It is concluded that multiple positive charges are involved during disturb to explain the observed extrinsic behavior. Its failure rate was improved with tunnel oxidation process tuning and stronger pre-oxidation cleans.

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2012 IEEE International Integrated Reliability Workshop Final Report

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