{"title":"基于PID的MOSFET测试结构布局对NBTI-、PBTI-和hcs寿命的影响","authors":"C. Schlunder, A. Martin","doi":"10.1109/IIRW.2012.6468926","DOIUrl":null,"url":null,"abstract":"We introduce and discuss in our paper an alternative to protection diodes and compare it with different sizes and placements of diodes. In contrast to other PID publications we do not focus on the PID itself but on the impact on full transistor-lifetime estimations. We evaluate long-term NBTI, PBTI and HCS experiments.","PeriodicalId":165120,"journal":{"name":"2012 IEEE International Integrated Reliability Workshop Final Report","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"On the impact of the layout of MOSFET test-structures on NBTI-, PBTI- and HCS-lifetime due to PID\",\"authors\":\"C. Schlunder, A. Martin\",\"doi\":\"10.1109/IIRW.2012.6468926\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We introduce and discuss in our paper an alternative to protection diodes and compare it with different sizes and placements of diodes. In contrast to other PID publications we do not focus on the PID itself but on the impact on full transistor-lifetime estimations. We evaluate long-term NBTI, PBTI and HCS experiments.\",\"PeriodicalId\":165120,\"journal\":{\"name\":\"2012 IEEE International Integrated Reliability Workshop Final Report\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE International Integrated Reliability Workshop Final Report\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IIRW.2012.6468926\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE International Integrated Reliability Workshop Final Report","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IIRW.2012.6468926","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
On the impact of the layout of MOSFET test-structures on NBTI-, PBTI- and HCS-lifetime due to PID
We introduce and discuss in our paper an alternative to protection diodes and compare it with different sizes and placements of diodes. In contrast to other PID publications we do not focus on the PID itself but on the impact on full transistor-lifetime estimations. We evaluate long-term NBTI, PBTI and HCS experiments.
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