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Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90.最新文献

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High speed polysilicon deposition process for dielectric isolation technology 用于介质隔离技术的高速多晶硅沉积工艺
Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90. Pub Date : 1990-04-04 DOI: 10.1109/ISPSD.1990.991080
S. Itoh, T. Usui, K. Akahane, N. Ishikawa, T. Yokoyama, Y. Maeda
{"title":"High speed polysilicon deposition process for dielectric isolation technology","authors":"S. Itoh, T. Usui, K. Akahane, N. Ishikawa, T. Yokoyama, Y. Maeda","doi":"10.1109/ISPSD.1990.991080","DOIUrl":"https://doi.org/10.1109/ISPSD.1990.991080","url":null,"abstract":"ABS\" This paper describes a newly developed high speed polysilicon deposition process in which molten silicon is sprayed on a substrate and solidified. By utilizing this process, a 500pn thick plysilicon layer which acts as a mechanical support of dielectrically isolated substrate was deposited in only a few minutes. Filling of the polysilicon in V-grooves, curvature of substrates, and dislocations induced in substrates are discussed. The characteristics of a high voltage LSI fabricated using this process is also described.","PeriodicalId":162198,"journal":{"name":"Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121450610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Small warpage dielectrically isolated wafer for power ICs by silicon wafer direct-bonding 用于功率集成电路的硅晶圆直接键合的小翘曲介质隔离晶圆
Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90. Pub Date : 1990-04-04 DOI: 10.1109/ISPSD.1990.991081
K. Furukawa, A. Nakagawa, K. Tanzawa, N. Kawamura
{"title":"Small warpage dielectrically isolated wafer for power ICs by silicon wafer direct-bonding","authors":"K. Furukawa, A. Nakagawa, K. Tanzawa, N. Kawamura","doi":"10.1109/ISPSD.1990.991081","DOIUrl":"https://doi.org/10.1109/ISPSD.1990.991081","url":null,"abstract":"The warpage mechanism was investigated for dielectlically isolated wafers, fabricated by the direct bonding. Three factors affecting the warpage were revealed. They were elastic deformation, a phenomenon peculiar to the direct bonding and poly-Si deposition. The investigation on these factors reduce the warpage to a few microns for 3 inch diameter wafers. Six inch diameter wafers were directly bonded to obtain 5 inch diameter SO1 wafers. The warpage for the SO1 wafer was 13 to 34 p. These results show that a 5 inch dielectlically isolated wafer can be applicable t o power IC fabrications.","PeriodicalId":162198,"journal":{"name":"Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114355728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A breakdown voltage simulator for semiconductor devices TonaddeIIb 半导体器件的击穿电压模拟器
Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90. Pub Date : 1990-04-04 DOI: 10.1109/ISPSD.1990.991053
I. Omura, A. Nakagawa
{"title":"A breakdown voltage simulator for semiconductor devices TonaddeIIb","authors":"I. Omura, A. Nakagawa","doi":"10.1109/ISPSD.1990.991053","DOIUrl":"https://doi.org/10.1109/ISPSD.1990.991053","url":null,"abstract":"A breakdown voltage simulator TONADDEDB has been developed for use to design high voltage device structures. It solves only the Poisson equation, thus attains rapid calculation. TONADDEIIB adopts new solution algorithm so that it can be applicable to the devices with lightly doped floating potential regions , which are depleted for a high voltage. TONADDEIIB can also calculate punchthrough current without solving the currentcontinuity equations using a new method.","PeriodicalId":162198,"journal":{"name":"Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90.","volume":"392 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132558147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High frequency reverse conducting GTO thyristor 高频反导GTO晶闸管
Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90. Pub Date : 1990-04-04 DOI: 10.1109/ISPSD.1990.991093
O. Yamada, M. Watanabe, H. Kakigi, T. Koga, Y. Takahashi, H. Kirihata
{"title":"High frequency reverse conducting GTO thyristor","authors":"O. Yamada, M. Watanabe, H. Kakigi, T. Koga, Y. Takahashi, H. Kirihata","doi":"10.1109/ISPSD.1990.991093","DOIUrl":"https://doi.org/10.1109/ISPSD.1990.991093","url":null,"abstract":"","PeriodicalId":162198,"journal":{"name":"Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124944362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Switching performances of enhanced gain bipolar mode field effect transistor (BMFET) 增强增益双极场效应晶体管(BMFET)的开关性能
Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90. Pub Date : 1990-04-04 DOI: 10.1109/ISPSD.1990.991095
G. Busatto, G. Ferla, P. Fallica, S. Musumeci
{"title":"Switching performances of enhanced gain bipolar mode field effect transistor (BMFET)","authors":"G. Busatto, G. Ferla, P. Fallica, S. Musumeci","doi":"10.1109/ISPSD.1990.991095","DOIUrl":"https://doi.org/10.1109/ISPSD.1990.991095","url":null,"abstract":"The switching performances of a new generation of normally-off BMFET with a sustaining voltage of 1600 V and current gain 5 at 6 Amp, obtained by improving gate transport parameters, are presented and compared to those of a bipolar junction transistor with same die size and sustaining voltage. Turn-off times as low as 58 ns are measured on these d,evices. The phenomena involved during the switching transient are investigated with the objective to study the effects of the variation of gate doping on the switching times.","PeriodicalId":162198,"journal":{"name":"Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124352186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High-voltage and power integrated circuits: switch topology, application and technology 高压与功率集成电路:开关拓扑、应用与技术
Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90. Pub Date : 1990-04-04 DOI: 10.1109/ISPSD.1990.991056
R.K. Williams
{"title":"High-voltage and power integrated circuits: switch topology, application and technology","authors":"R.K. Williams","doi":"10.1109/ISPSD.1990.991056","DOIUrl":"https://doi.org/10.1109/ISPSD.1990.991056","url":null,"abstract":"The partitioning of an intelligent-power electronic system into one or more semiconductor components is both application and technology specific. Overall system cost, chip area and packaging considerations along with power, on-resistance, off-state blocking capabiliv, speed and switch-load topology determine the technical and economic fern-bility of a given technology and partitioning approach. Emerging trends in the use of self-isolated, conventional and RESURF junction-isolated, and dielectrically-isolatedprocess technologies needed to .address applications employing low-side switch topologies for single-quadrant power converters, LV pushpull topologies for disk drives, monolithic HV PIP topologies for display driven, multichip HV PIP topologies comn to off-line motor control, and high-side switch topologies used in automotive electronics are detailed.","PeriodicalId":162198,"journal":{"name":"Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90.","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117209486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
High power transistor modules with intelligent functions 具有智能化功能的大功率晶体管模块
Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90. Pub Date : 1990-04-04 DOI: 10.1109/ISPSD.1990.991076
H. Shisekane, T. Hosen, N. Terasawa, K. Kuwabara, Y. Inakoshi
{"title":"High power transistor modules with intelligent functions","authors":"H. Shisekane, T. Hosen, N. Terasawa, K. Kuwabara, Y. Inakoshi","doi":"10.1109/ISPSD.1990.991076","DOIUrl":"https://doi.org/10.1109/ISPSD.1990.991076","url":null,"abstract":"This paper presents high power transistor modules with intelligent functions such as self-protection and self-diagnosis. The current capacity of the modules rangesfrom 30A to 150A. Two key technologies for high power intelligent modules with compact size are reported. One is the development of power transistor chips (high hpE transistors and low loss IGBTs) and the other is the development of new module packages. This is the first demonstration of intelligent power modules more than 50A current capacity.","PeriodicalId":162198,"journal":{"name":"Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127017744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
12kV, 1kA thyristor
Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90. Pub Date : 1990-04-04 DOI: 10.1109/ISPSD.1990.991097
H. Iwamoto, T. Nakagawa, F. Tokunoh, A. Tada, Y. Yamauchi, M. Yamamoto, K. Satoh
{"title":"12kV, 1kA thyristor","authors":"H. Iwamoto, T. Nakagawa, F. Tokunoh, A. Tada, Y. Yamauchi, M. Yamamoto, K. Satoh","doi":"10.1109/ISPSD.1990.991097","DOIUrl":"https://doi.org/10.1109/ISPSD.1990.991097","url":null,"abstract":"The u l t r a h i g h b l o c k i n g v o l t a g e t h y r i s t o r w i t h b l o c k i n g v o l t a g e s of 12kV and t h e a v e r a g e o n s t a t e c u r r e n L of 1kA w a s r e a l i z e d . I n o r d e r t o o b L a i n h i g h b l o c k i n g v o l l a g e s and t h e low on-sLaLe v o l t a g e , d i f f u s i o n p r o c e s s e s and t h e g a t e and c a t h o d e s L r u c L u r e were o p t i m i z e d and t h e f u l l p r e s s u r e c o n t a c l s t r u c l u r e w a s employed. T h i s p a p e r e x p l a i n s t h e s t r u c t u r e and t h e e l e c t r i c a l c h a r a c L e r i s t i c s o f t h i s d e v i c e .","PeriodicalId":162198,"journal":{"name":"Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90.","volume":"2017 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127552542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Latching in N-channel, high-voltage hybrid SINFET's 在n通道，高压混合SINFET的锁存
Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90. Pub Date : 1990-04-04 DOI: 10.1109/ISPSD.1990.991069
T. Chow, D. Pattanayak, B. J. Baliga, M. Adler
{"title":"Latching in N-channel, high-voltage hybrid SINFET's","authors":"T. Chow, D. Pattanayak, B. J. Baliga, M. Adler","doi":"10.1109/ISPSD.1990.991069","DOIUrl":"https://doi.org/10.1109/ISPSD.1990.991069","url":null,"abstract":"The latching characteristics of 500V, n-channel HSINFET's are measured and compared to lateral IGBT's with and without collector shorts. In particular, the effect of substrate resistivity, Schottky region length in the collector and emitter shorts on latching suppression are studied. Also, latching or maximum gate controlled current at elevated temperatures up to 150 C is measured. While the HSINFET's are superior to the corresponding collector-shorted LIGBT's in latching, but inferior to the LIGBT's without collector shorts.","PeriodicalId":162198,"journal":{"name":"Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115775994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
New 500V output device structures for thin silicon layer on silicon dioxide film 新型二氧化硅薄膜上硅薄层500V输出器件结构
Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90. Pub Date : 1990-04-04 DOI: 10.1109/ISPSD.1990.991067
A. Nakagawa, N. Yasuhara, Y. Baba
{"title":"New 500V output device structures for thin silicon layer on silicon dioxide film","authors":"A. Nakagawa, N. Yasuhara, Y. Baba","doi":"10.1109/ISPSD.1990.991067","DOIUrl":"https://doi.org/10.1109/ISPSD.1990.991067","url":null,"abstract":"Studies into a 20 w deep trench technique for dielectric isolation and a high voltage lateral device structure for thin silicon layers have been carried out. These techniques can be applied to high voltage power ICs with high density packing. These proposed structures are characterized by a very shallow N-type diffusion layer on a bottom film of relatively thick silicon dioxide. Breakdown simulation was carried out by means of the two-dimensional device simulator TONADDEIIB. It was shown that a breakdown voltage of more than 500 V can be obtained with a 20 thick silicon layer structure.","PeriodicalId":162198,"journal":{"name":"Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90.","volume":"93 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127983182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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