2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)最新文献_第3页

Fast/sub 14/ Technology: design technology for the automation of multi-gigahertz digital logic Fast/sub 14/ Technology:用于多千兆赫数字逻辑自动化的设计技术

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309937

S. Horne, D. Glowka, S. McMahon, P. Nixon, M. Seningen, G. Vijayan

{"title":"Fast/sub 14/ Technology: design technology for the automation of multi-gigahertz digital logic","authors":"S. Horne, D. Glowka, S. McMahon, P. Nixon, M. Seningen, G. Vijayan","doi":"10.1109/ICICDT.2004.1309937","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309937","url":null,"abstract":"Fast/sub 14/ Technology automates the implementation of multi-GHz digital logic circuits in standard CMOS fabrication processes. Fast/sub 14/ Technology derives its name from the atomic number of silicon (which translates to \"Fast Silicon Technology\"). Fast/sub 14/ Technology is comprised of five critical design elements: Multiphase Overlapped Clocking; 1-of-N Dynamic Logic (NDO family); Expert Routing Technology/sup TM/; Unified Design Database; Design Methodology and Electronic Design Automation (EDA) Tools Suite. Fast/sub 14/ Technology enables a significant improvement in chip design productivity for high-speed digital logic. Fast/sub 14/ Technology also provides significant power and silicon area efficiency benefits over other design methodologies in the high-performance logic design space. These benefits enable embedded processors and special-purpose digital logic products to achieve the levels of performance previously achieved only through custom design flows while maintaining efficient levels of power. These high performance levels are achieved at greatly reduced development costs and with lower risk of circuit problems as compared to the custom design flows used for desktop processors.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124922356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Flexible threshold voltage 4-terminal FinFETs 灵活的阈值电压4端finfet

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309915

Yongxun Liu, M. Masahara, K. Ishii, E. Suzuki

引用次数: 1

Deep-submicron design challenges for a dual-core 64b UltraSPARC microprocessor implementation 双核64b UltraSPARC微处理器实现的深亚微米设计挑战

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309933

T. Takayanagi, J. L. Shin, J. Su, A. Leon

引用次数: 2

Breakdown transients in ultra-thin gate oxynitrides 超薄栅氮氧化物的击穿瞬态

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309982

S. Lombardo, F. Palumbo, J. Stathis, B. Linder, K. Pey, C. Tung

引用次数: 2

Advanced SOI substrate manufacturing 先进的SOI衬底制造

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309919

C. Mazure, G. Celler, C. Maleville, I. Cayrefourcq

引用次数: 4

Plasma damage considerations involving metal-insulator-metal (MIM) capacitors 涉及金属-绝缘体-金属(MIM)电容器的等离子体损伤考虑

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309925

B. O'Connell, T. Thibeault, P. Chaparala

引用次数: 5

Can TDDB continue to serve as reliability test method for advance gate dielectric? TDDB能否继续作为超前栅介质的可靠性测试方法?

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309979

K. Cheung

引用次数: 2

Advanced device structure for aggressively scaled MOSFETs 用于大规模缩放mosfet的先进器件结构

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309908

T. Hirarnoto

引用次数: 0

Impact of process scaling on the efficacy of leakage reduction schemes 工艺尺度对减少泄漏方案效果的影响

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309890

Y. Tsai, David Duartep, N. Vijaykrishnan, M. J. Irwin

引用次数: 2

Maximum clock frequency distribution model with practical VLSI design considerations 具有实际VLSI设计考虑的最大时钟频率分布模型

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309942

K. Bowman, S. Samaan, N. Hakim

{"title":"Maximum clock frequency distribution model with practical VLSI design considerations","authors":"K. Bowman, S. Samaan, N. Hakim","doi":"10.1109/ICICDT.2004.1309942","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309942","url":null,"abstract":"A previous model derivation of the maximum clock frequency (FMAX) distribution for a VLSI design is reviewed to enable pre-silicon predictions of frequency bins and process/design optimization for specific product targets. Model projections were compared with measured FMAX data for a 0.25/spl mu/m microprocessor. In this paper, an additional comparison is performed with a 0.13/spl mu/m microprocessor, illustrating the close agreement between the simulated and measured distributions in mean, variance, and shape for different values of temperature and supply voltage. The previous model revealed that within-die variations primarily reduce the mean FMAX, or reciprocally, increase the mean of the maximum critical path delay (T/sub cp,max/) distribution. In this paper, a closed-form analytical equation of the T/sub cp,max/ mean increase is derived as an extension to the FMAX distribution model, which further elucidates the dependency on within-die variations. For a given set of process- and circuit-level parameters, this model provides insight into the delay guard-band required to achieve specific performance goals. Moreover, the model identifies the point of diminishing returns for redesigning critical paths in the tail of the timing histogram. To explore the region of validity, a model assumption for the shape of the critical path delay distribution is examined to guide practical VLSI design decisions.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133608825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17