用于大规模缩放mosfet的先进器件结构

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI:10.1109/ICICDT.2004.1309908

T. Hirarnoto

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引用次数: 0

摘要

在本文中，我们介绍了我们最近在10纳米尺度上的器件结构的研究工作。考虑到在纳米尺度下的短通道抗扰性，我们选择了完全耗尽的SOI结构，包括双栅结构和finfet。从短通道效应、低功耗和器件特性波动等方面讨论了器件的最佳结构。提出了“体效意识”装置设计思想。

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Advanced device structure for aggressively scaled MOSFETs

In this paper, we present our recent research work on device structures in the 10 nm scale. Considering the short channel immunity in the nanoscale regime, the fully-depleted SOI structures, including double-gate structures and FinFETs, have been selected. The optimum device structures have been discussed in terms of short channel effect, low power, and device characteristic fluctuations. The idea of "body-effect conscious" device design is proposed.

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2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)

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