2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)最新文献

Optimization and scaling limit forecast of nitrided gate oxide using an equivalent nitride/oxide (N/O) stack model 基于等效氮化物/氧化物(N/O)堆模型的氮化栅极氧化物优化及结垢极限预测

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309983

V. Chang, C. Chen, Y. Jin, C. Chen, T. Lee, S. Chen, M. Liang

引用次数: 2

PRAM process technology PRAM工艺技术

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309906

G. Koh, Y. Hwang, Sun-Ghil Lee, Suyoun Lee, K. Ryoo, Joon-Min Park, Yun-Heub Song, Soomin Ahn, Changwook Jeong, F. Yeung, Y. Kim, J.-B. Park, G. Jeong, H. Jeong, Keunnam Kim

引用次数: 9

Analysis of plasma damage on phase change memory cells 相变记忆细胞的等离子损伤分析

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309950

F. Pellizzer, A. Spandre, S. Alba, A. Pirovano

引用次数: 1

Statistical design for variation tolerance: key to continued Moore's law 变异容差的统计设计:延续摩尔定律的关键

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309939

T. Karnik, Vivek De, S. Borkar, T. Karnik

引用次数: 31

Monte-Carlo simulation of the effects of vacuum ultraviolet radiation on electronic materials 真空紫外辐射对电子材料影响的蒙特卡罗模拟

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309977

G. Upadhyaya, J.L. Shohet, J.L. Lauer

{"title":"Monte-Carlo simulation of the effects of vacuum ultraviolet radiation on electronic materials","authors":"G. Upadhyaya, J.L. Shohet, J.L. Lauer","doi":"10.1109/ICICDT.2004.1309977","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309977","url":null,"abstract":"Radiation induced damage during the plasma processing of semiconductor materials adversely affects device reliability. Our group has shown in the past that Vacuum Ultraviolet (VUV) radiation (10nm-200nm) can beneficially deplete the charge deposited on the surface of the semiconductor by temporarily increasing the conductivity of the dielectric. The increase in conductivity has mainly been attributed to the generation of photoemission current and formation of electron hole pairs in the dielectric. In this paper, we discuss the steps involved in developing a model for VUV-semiconductor dielectric interactions based on the well-known Monte Carlo method. The statistical information obtained from this simulation will be compared to the experimental values obtained by exposing silicon nitride wafers to synchrotron radiation of energy 20eV. The simulation predicts the surface potential on the wafer due to photoemission. Experimentally measured surface potentials on the dielectric are used to check the validity of the simulation. Of the different process that can occur when a photon is incident on an atom, we concentrate mainly on photoemission of an electron. Consequently, the elastic and inelastic scattering events experienced by the electron during the course of its motion inside the dielectric are also considered. A modified form of the screened Rutherford formula, which approximates the Mott cross-section, as developed by Browning et. al., has been applied in this simulation. Initial simulation results will be presented.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123864685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Prospects of emerging new memory technologies 新兴存储技术的前景

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309904

Sung-young Lee, Keunwoo Kim

引用次数: 5

Recent developments in high-performance system-on-chip IC design 高性能片上系统集成电路设计的最新进展

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309934

A. Khan

{"title":"Recent developments in high-performance system-on-chip IC design","authors":"A. Khan","doi":"10.1109/ICICDT.2004.1309934","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309934","url":null,"abstract":"Chip designers transitioning from VLSI to System-on-Chip (SoC) design are experiencing a major increase in design complexity: Project scale, design content and the technical requirements for successful design are all going up concurrently and, in many cases, exponentially. At the same time, business success increasingly requires first-to-market delivery of innovative and competitive new products with rapid ramp to volume production. In many cases, the manufacturing life of individual designs is trending downwards, from many years to (typically) about one year. Conventional design approaches - which evolved over time to address VLSI design requirements - often do not scaleup to address requirements in this era of nanometer SoCs. At a practical level, this may result in multiple silicon iterations to address all of the product requirements correctly, which is likely to jeopardize business success in the present stringent business climate: There is simply not enough time to iterate-to-success and still achieve business goals. These two forces increasing design complexity and reduced manufacturing windows - place a great (and growing) emphasis on achieving first silicon success with high-yielding designs; this is increasingly the key difference between business success and failure for SoC design. The presentation focuses on sharing recent design experience in developing several, industry-first system-on-chip (SoC) ICs, as these relate to improvements in design methods (including design best practices to verify design performance across the manufacturing range), new design technologies, design methodology, and circuit and chip electrical / physical design techniques which contributed to first silicon success. The results enabled successful achievement of business and technical objectives set for the designs. The material may be useful for design engineers and general / technical management interested in the design and development of nanometer system-on-chip ICs.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133492088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Design aspects of a 4 Mbit 0.18 /spl mu/m 1T1MTJ toggle MRAM memory 设计方面的4 Mbit 0.18 /spl mu/m 1T1MTJ切换MRAM存储器

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309940

Chitra K. Subramanian, T. Andre, J. Nahas, B. Garni, H. Lin, A. Omair, W. Martino

引用次数: 3

Radiation assurance for the space environment 空间环境辐射保障

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309976

Janet L Barth, Kenneth A Ieee, eee Christian Label, Poivey

引用次数: 34

Investigation of nano interconnects for an early experimental assessment of future interconnect challenges 研究纳米互连对未来互连挑战的早期实验评估

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309921

N. Engelhardt, G. Schindler, W. Steinhogl, G. Steinlesberger, M. Traving

{"title":"Investigation of nano interconnects for an early experimental assessment of future interconnect challenges","authors":"N. Engelhardt, G. Schindler, W. Steinhogl, G. Steinlesberger, M. Traving","doi":"10.1109/ICICDT.2004.1309921","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309921","url":null,"abstract":"The investigation of interconnects with CDs of future technology nodes is limited to direct writing techniques for pattern definition, as next generation lithography is still under investigation. To by-pass the throughput limitations of direct writing, allowing the fabrication of only a limited number of test structures for process adaptations and electrical characterization, alternative approaches were developed. Standard stepper manufacturing lithography was used in combination with additional process tricks to fabricate a large number of test structures across the wafers with CDs down to 20nm, however, at the expense of a relaxed pitch. For a study of the scaling limits of copper damascene and subtractive aluminium metallization, a removable spacer technique and a hard mask trim were developed, respectively. Thus damascene trenches and RIE-masks with deep sub-100nm CDs could be prepared. The electrical characterization of Cu nano interconnects shows that the ITRS requirement for the conductor resistivity will not be met, not even with cooling, in future technology generations. The ITRS red brick wall for barrier films, however, is getting cracks. Barrier functionality with film thicknesses below end-of-roadmap thickness requirements was demonstrated with excellent barrier integrity regarding line-to-line leakage after anneals and after excessive BTS tests. First results on electromigration behaviour of Cu nano interconnects are also encouraging. Results on Al are underway.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124436337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4