2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)最新文献_第2页

Advanced flash memory reliability 先进的闪存可靠性

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309947

A. Modelli, A. Visconti, R. Bez

引用次数: 26

Time evolution of V/sub TH/ distribution under BT stress in ultra-thin gate oxides 超薄栅极氧化物在BT应力下V/亚TH/分布的时间演化

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309978

Y. Mitani, H. Satake

引用次数: 0

Thin oxide degradation from HDP-CVD oxide deposition in 300mm process HDP-CVD氧化沉积300mm工艺降解薄氧化物

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309980

Si-Woo Lee, Changmoon Ahn, B. Kim, S. Chang, D.H. Han, C. An, J. Won, Jaeyoung Kim, Seungwook Jung, Dongho-Shin, Kyungseok Oh, Won-seong Lee, Donggun Park

引用次数: 3

Film properties and integration performance of carbon doped oxides 碳掺杂氧化物的薄膜性能及集成性能

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309922

Hichem MSaad

{"title":"Film properties and integration performance of carbon doped oxides","authors":"Hichem MSaad","doi":"10.1109/ICICDT.2004.1309922","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309922","url":null,"abstract":"Summary form only given. The semiconductor industry has witnessed a successful introduction of copper based interconnects and low permittivity insulators with 130nm node devices. The advent of 90nm node devices has led to the introduction of first generation of carbon doped dielectric films. Further scaling will require materials with lower permittivity and this has accelerated the development of a second generation of carbon doped oxides with imbedded porosity. While the addition of carbon to a silicon based dielectric lowers the permittivity of the insulator, carbon doping may also lead to degradation in the surface properties of such films. Frequently, carbon enrichment at surfaces is known to cause issues with the wetting characteristics of the surface. In addition, the mechanical strength of interfaces formed with carbon enriched surfaces may be poor compared to congruent surfaces. The high number of chemically and morphologically different materials in the integrated interconnects structure increase the possibility of mechanical structural failure. A detailed understanding of the basic material properties and the behavior of the carbon doped materials during subsequent processing is therefore of prime importance. This paper will present an overview of process and film property characterization of different generations of carbon doped oxides. Integration properties of these films and correlation to processing parameters and physical properties of the materials will be discussed. Novel processing techniques are discussed that enable the implementation of advanced low dielectric constant materials without sacrificing the high volume manufacturability of such films.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121825129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reducing FHDP plasma induced damage with silicon-rich oxide and oxynitride barrier layers 用富硅氧化物和氮化氧阻挡层减少FHDP等离子体引起的损伤

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309965

H. McCulloh, B. O'Connell, S. Drizlikh, D. Brisbin

引用次数: 5

An embedded silicon nanocrystal nonvolatile memory for the 90nm technology node operating at 6V 一种用于工作电压为6V的90nm技术节点的嵌入式硅纳米晶非易失性存储器

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309900

R. Muralidhar, R. Steimle, M. Sadd, R. Rao, C. Swift, E. Prinz, J. Yater, L. Grieve, K. Harber, B. Hradsky, S. Straub, B. Acred, W. Paulson, W. Chen, L. Parker, S. Anderson, M. Rossow, T. Merchant, M. Paransky, T. Huynh, D. Hadad, Ko-Min Chang, B. White

{"title":"An embedded silicon nanocrystal nonvolatile memory for the 90nm technology node operating at 6V","authors":"R. Muralidhar, R. Steimle, M. Sadd, R. Rao, C. Swift, E. Prinz, J. Yater, L. Grieve, K. Harber, B. Hradsky, S. Straub, B. Acred, W. Paulson, W. Chen, L. Parker, S. Anderson, M. Rossow, T. Merchant, M. Paransky, T. Huynh, D. Hadad, Ko-Min Chang, B. White","doi":"10.1109/ICICDT.2004.1309900","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309900","url":null,"abstract":"This paper reports on the first functional 6V, 4Mb silicon nanocrystal based nonvolatile memory array using conventional 90nm and 0.25/spl mu/m process technologies. The silicon nanocrystal based NOR Flash can be programmed and erased using conventional techniques in floating gate memories. Key aspects of this technology are the ability to form nanocrystals of the right size and density, the ability to protect them from subsequent processing effects and the ability to remove them from undesired areas. The use of isolated silicon nanocrystals for charge storage provides the opportunity to reduce the program and erase voltages due to tunnel oxide scaling and also has potential for two bits/cell operation. Optimization of tunnel and control oxides is critical to obtain high program/erase cycling endurance. Due to the area savings from memory module peripheral voltage scaling and the reduction in mask count over conventional floating gate technology, silicon nanocrystal non-volatile memory technology can substantially reduce the cost of embedded flash at the 90nm technology node and beyond.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131126436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

SOI charging prevention: chip-level net tracing and diode protection SOI充电预防:芯片级网络跟踪和二极管保护

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309926

T. Hook, H. Bonges, D. Harmon, W. Lai

引用次数: 3

Advanced germanium MOSFET technologies with high-/spl kappa/ gate dielectrics and shallow junctions 先进的锗MOSFET技术，具有高/spl kappa/栅极电介质和浅结

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309955

C. O. Chui, K. Saraswat

引用次数: 6

A 0.18 /spl mu/m 4 Mbit toggling MRAM 一个0.18 /spl mu/m 4 Mbit可切换MRAM

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309899

M. Durlam, D. Addie, J. Åkerman, B. Butcher, P. Brown, J. Chan, M. Deherrera, B. Engel, B. Feil, G. Grynkewich, J. Janesky, M. Johnson, K. Kyler, J. Molla, J. Martin, K. Nagel, J. Nahas, J. Ren, N. Rizzo, T. Rodriguez, L. Savtchenko, J. Salter, J. Slaughter, K. Smith, J.J. Sun, M. Lien, K. Papworth, P. Shah, W. Qin, R. Williams, L. Wise, S. Tehrani

引用次数: 3

Advanced double-gate fully-depleted silicon-on-insulator (DG-FDSOI) device and device impact on circuit design & power management 先进的双栅全耗尽绝缘体上硅(DG-FDSOI)器件及其对电路设计和电源管理的影响

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309917

T. Dao

引用次数: 5