一种用于工作电压为6V的90nm技术节点的嵌入式硅纳米晶非易失性存储器

R. Muralidhar, R. Steimle, M. Sadd, R. Rao, C. Swift, E. Prinz, J. Yater, L. Grieve, K. Harber, B. Hradsky, S. Straub, B. Acred, W. Paulson, W. Chen, L. Parker, S. Anderson, M. Rossow, T. Merchant, M. Paransky, T. Huynh, D. Hadad, Ko-Min Chang, B. White
{"title":"一种用于工作电压为6V的90nm技术节点的嵌入式硅纳米晶非易失性存储器","authors":"R. Muralidhar, R. Steimle, M. Sadd, R. Rao, C. Swift, E. Prinz, J. Yater, L. Grieve, K. Harber, B. Hradsky, S. Straub, B. Acred, W. Paulson, W. Chen, L. Parker, S. Anderson, M. Rossow, T. Merchant, M. Paransky, T. Huynh, D. Hadad, Ko-Min Chang, B. White","doi":"10.1109/ICICDT.2004.1309900","DOIUrl":null,"url":null,"abstract":"This paper reports on the first functional 6V, 4Mb silicon nanocrystal based nonvolatile memory array using conventional 90nm and 0.25/spl mu/m process technologies. The silicon nanocrystal based NOR Flash can be programmed and erased using conventional techniques in floating gate memories. Key aspects of this technology are the ability to form nanocrystals of the right size and density, the ability to protect them from subsequent processing effects and the ability to remove them from undesired areas. The use of isolated silicon nanocrystals for charge storage provides the opportunity to reduce the program and erase voltages due to tunnel oxide scaling and also has potential for two bits/cell operation. Optimization of tunnel and control oxides is critical to obtain high program/erase cycling endurance. Due to the area savings from memory module peripheral voltage scaling and the reduction in mask count over conventional floating gate technology, silicon nanocrystal non-volatile memory technology can substantially reduce the cost of embedded flash at the 90nm technology node and beyond.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"An embedded silicon nanocrystal nonvolatile memory for the 90nm technology node operating at 6V\",\"authors\":\"R. Muralidhar, R. Steimle, M. Sadd, R. Rao, C. Swift, E. Prinz, J. Yater, L. Grieve, K. Harber, B. Hradsky, S. Straub, B. Acred, W. Paulson, W. Chen, L. Parker, S. Anderson, M. Rossow, T. Merchant, M. Paransky, T. Huynh, D. Hadad, Ko-Min Chang, B. White\",\"doi\":\"10.1109/ICICDT.2004.1309900\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper reports on the first functional 6V, 4Mb silicon nanocrystal based nonvolatile memory array using conventional 90nm and 0.25/spl mu/m process technologies. The silicon nanocrystal based NOR Flash can be programmed and erased using conventional techniques in floating gate memories. Key aspects of this technology are the ability to form nanocrystals of the right size and density, the ability to protect them from subsequent processing effects and the ability to remove them from undesired areas. The use of isolated silicon nanocrystals for charge storage provides the opportunity to reduce the program and erase voltages due to tunnel oxide scaling and also has potential for two bits/cell operation. Optimization of tunnel and control oxides is critical to obtain high program/erase cycling endurance. Due to the area savings from memory module peripheral voltage scaling and the reduction in mask count over conventional floating gate technology, silicon nanocrystal non-volatile memory technology can substantially reduce the cost of embedded flash at the 90nm technology node and beyond.\",\"PeriodicalId\":158994,\"journal\":{\"name\":\"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-10-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICDT.2004.1309900\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2004.1309900","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11

摘要

本文报道了第一个功能性的6V, 4Mb硅纳米晶非易失性存储阵列,采用传统的90nm和0.25/spl mu/m工艺技术。基于硅纳米晶体的NOR闪存可以在浮动门存储器中使用传统技术进行编程和擦除。这项技术的关键方面是形成合适尺寸和密度的纳米晶体的能力,保护它们免受后续加工影响的能力,以及将它们从不需要的区域移除的能力。使用隔离的硅纳米晶体进行电荷存储,可以减少由于隧道氧化结垢导致的程序和擦除电压,并且还具有2位/单元操作的潜力。隧道和控制氧化物的优化是获得高程序/擦除循环耐久性的关键。由于与传统浮栅技术相比,存储模块外围电压缩放节省了面积,并且减少了掩模数量,因此硅纳米晶非易失性存储技术可以大幅降低90纳米及以上技术节点的嵌入式闪存成本。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An embedded silicon nanocrystal nonvolatile memory for the 90nm technology node operating at 6V
This paper reports on the first functional 6V, 4Mb silicon nanocrystal based nonvolatile memory array using conventional 90nm and 0.25/spl mu/m process technologies. The silicon nanocrystal based NOR Flash can be programmed and erased using conventional techniques in floating gate memories. Key aspects of this technology are the ability to form nanocrystals of the right size and density, the ability to protect them from subsequent processing effects and the ability to remove them from undesired areas. The use of isolated silicon nanocrystals for charge storage provides the opportunity to reduce the program and erase voltages due to tunnel oxide scaling and also has potential for two bits/cell operation. Optimization of tunnel and control oxides is critical to obtain high program/erase cycling endurance. Due to the area savings from memory module peripheral voltage scaling and the reduction in mask count over conventional floating gate technology, silicon nanocrystal non-volatile memory technology can substantially reduce the cost of embedded flash at the 90nm technology node and beyond.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信