Recent developments in high-performance system-on-chip IC design

A. Khan
{"title":"Recent developments in high-performance system-on-chip IC design","authors":"A. Khan","doi":"10.1109/ICICDT.2004.1309934","DOIUrl":null,"url":null,"abstract":"Chip designers transitioning from VLSI to System-on-Chip (SoC) design are experiencing a major increase in design complexity: Project scale, design content and the technical requirements for successful design are all going up concurrently and, in many cases, exponentially. At the same time, business success increasingly requires first-to-market delivery of innovative and competitive new products with rapid ramp to volume production. In many cases, the manufacturing life of individual designs is trending downwards, from many years to (typically) about one year. Conventional design approaches - which evolved over time to address VLSI design requirements - often do not scaleup to address requirements in this era of nanometer SoCs. At a practical level, this may result in multiple silicon iterations to address all of the product requirements correctly, which is likely to jeopardize business success in the present stringent business climate: There is simply not enough time to iterate-to-success and still achieve business goals. These two forces increasing design complexity and reduced manufacturing windows - place a great (and growing) emphasis on achieving first silicon success with high-yielding designs; this is increasingly the key difference between business success and failure for SoC design. The presentation focuses on sharing recent design experience in developing several, industry-first system-on-chip (SoC) ICs, as these relate to improvements in design methods (including design best practices to verify design performance across the manufacturing range), new design technologies, design methodology, and circuit and chip electrical / physical design techniques which contributed to first silicon success. The results enabled successful achievement of business and technical objectives set for the designs. The material may be useful for design engineers and general / technical management interested in the design and development of nanometer system-on-chip ICs.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2004.1309934","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10

Abstract

Chip designers transitioning from VLSI to System-on-Chip (SoC) design are experiencing a major increase in design complexity: Project scale, design content and the technical requirements for successful design are all going up concurrently and, in many cases, exponentially. At the same time, business success increasingly requires first-to-market delivery of innovative and competitive new products with rapid ramp to volume production. In many cases, the manufacturing life of individual designs is trending downwards, from many years to (typically) about one year. Conventional design approaches - which evolved over time to address VLSI design requirements - often do not scaleup to address requirements in this era of nanometer SoCs. At a practical level, this may result in multiple silicon iterations to address all of the product requirements correctly, which is likely to jeopardize business success in the present stringent business climate: There is simply not enough time to iterate-to-success and still achieve business goals. These two forces increasing design complexity and reduced manufacturing windows - place a great (and growing) emphasis on achieving first silicon success with high-yielding designs; this is increasingly the key difference between business success and failure for SoC design. The presentation focuses on sharing recent design experience in developing several, industry-first system-on-chip (SoC) ICs, as these relate to improvements in design methods (including design best practices to verify design performance across the manufacturing range), new design technologies, design methodology, and circuit and chip electrical / physical design techniques which contributed to first silicon success. The results enabled successful achievement of business and technical objectives set for the designs. The material may be useful for design engineers and general / technical management interested in the design and development of nanometer system-on-chip ICs.
高性能片上系统集成电路设计的最新进展
从超大规模集成电路(VLSI)过渡到片上系统(SoC)设计的芯片设计人员正经历着设计复杂性的大幅增加:项目规模、设计内容和成功设计的技术要求都在同时上升,在许多情况下,呈指数级增长。与此同时,企业的成功越来越需要将创新的、有竞争力的新产品率先推向市场,并迅速实现批量生产。在许多情况下,单个设计的制造寿命呈下降趋势,从多年降至(通常)一年左右。传统的设计方法——随着时间的推移而发展,以满足超大规模集成电路的设计要求——通常不能扩展到满足纳米soc时代的要求。在实际层面上,这可能会导致多次硅迭代来正确地处理所有的产品需求,这可能会危及当前严格的业务环境中的业务成功:根本没有足够的时间来迭代成功并仍然实现业务目标。这两种力量增加了设计的复杂性和减少了制造窗口-将高度(并且日益)强调实现高产量设计的第一个硅的成功;这日益成为SoC设计商业成功与失败之间的关键区别。本次演讲的重点是分享最近在开发几个业界首个系统级芯片(SoC) ic方面的设计经验,因为这些涉及到设计方法的改进(包括在制造范围内验证设计性能的设计最佳实践),新设计技术,设计方法以及电路和芯片电气/物理设计技术,这些都有助于首次硅的成功。结果能够成功地实现为设计设定的业务和技术目标。该材料可能对设计工程师和对纳米片上系统集成电路的设计和开发感兴趣的一般/技术管理人员有用。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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