Design aspects of a 4 Mbit 0.18 /spl mu/m 1T1MTJ toggle MRAM memory

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI:10.1109/ICICDT.2004.1309940

Chitra K. Subramanian, T. Andre, J. Nahas, B. Garni, H. Lin, A. Omair, W. Martino

引用次数: 3

Abstract

A 4 Mbit "Toggle" MRAM, built in 0.18 micron five level metal CMOS technology, using a 1.55 /spl mu/m/sup 2/ bitcell with a single toggling magneto tunnel junction is described. The "Toggle" memory uses unidirectional programming currents controlled by switched local mirror circuits to achieve robust write operation. The isolated read architecture supports a 25 ns asynchronous cycle time operation, driven by balanced three input current mirror sense amplifiers.

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设计方面的4 Mbit 0.18 /spl mu/m 1T1MTJ切换MRAM存储器

介绍了一种采用0.18微米五级金属CMOS技术的4 Mbit“Toggle”MRAM，该MRAM采用1.55 /spl mu/m/sup 2/ bit单元，具有单个切换磁通隧道结。“切换”存储器使用由切换的本地镜像电路控制的单向编程电流来实现稳健的写操作。隔离读结构支持25 ns异步周期时间操作，由平衡的三个输入电流镜像感测放大器驱动。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)

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