双核64b UltraSPARC微处理器实现的深亚微米设计挑战

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI:10.1109/ICICDT.2004.1309933

T. Takayanagi, J. L. Shin, J. Su, A. Leon

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引用次数: 2

摘要

处理器核心最初设计为0.5/spl mu/m Al进程，重新设计为0.13/spl mu/m Cu进程，以创建具有1MB集成L2缓存的双核处理器，为计算密集的服务器应用程序提供高效的性能与功率比。讨论了电路设计挑战，包括负偏置温度不稳定性(NBTI)、泄漏、耦合噪声和模内工艺变化。

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Deep-submicron design challenges for a dual-core 64b UltraSPARC microprocessor implementation

A processor core, originally designed in a 0.5/spl mu/m Al process, is redesigned for a 0.13/spl mu/m Cu process to create a dual-core processor with 1MB integrated L2 cache, offering an efficient performance to power ratio for compute-dense server applications. Circuit design challenges, including negative bias temperature instability (NBTI), leakage, coupling noise and intra die process variation are discussed.

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来源期刊

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)

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