Fast/sub 14/ Technology:用于多千兆赫数字逻辑自动化的设计技术

S. Horne, D. Glowka, S. McMahon, P. Nixon, M. Seningen, G. Vijayan
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引用次数: 14

摘要

Fast/sub 14/ Technology在标准CMOS制造工艺中自动化实现多ghz数字逻辑电路。Fast/sub 14/ Technology的名字来源于硅的原子序数(翻译过来就是“快速硅技术”)。Fast/sub 14/ Technology由五个关键设计元素组成:多相重叠时钟;1-of-N动态逻辑;专家路由技术/sup TM;统一设计数据库;设计方法论和电子设计自动化(EDA)工具套件。Fast/sub 14/技术可以显著提高高速数字逻辑的芯片设计效率。与高性能逻辑设计领域的其他设计方法相比,Fast/sub 14/技术还提供了显著的功率和硅面积效率优势。这些优势使嵌入式处理器和专用数字逻辑产品能够实现以前只有通过定制设计流程才能实现的性能水平,同时保持高效的功耗水平。与用于桌面处理器的定制设计流程相比,这些高性能水平以大大降低的开发成本和更低的电路问题风险实现。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Fast/sub 14/ Technology: design technology for the automation of multi-gigahertz digital logic
Fast/sub 14/ Technology automates the implementation of multi-GHz digital logic circuits in standard CMOS fabrication processes. Fast/sub 14/ Technology derives its name from the atomic number of silicon (which translates to "Fast Silicon Technology"). Fast/sub 14/ Technology is comprised of five critical design elements: Multiphase Overlapped Clocking; 1-of-N Dynamic Logic (NDO family); Expert Routing Technology/sup TM/; Unified Design Database; Design Methodology and Electronic Design Automation (EDA) Tools Suite. Fast/sub 14/ Technology enables a significant improvement in chip design productivity for high-speed digital logic. Fast/sub 14/ Technology also provides significant power and silicon area efficiency benefits over other design methodologies in the high-performance logic design space. These benefits enable embedded processors and special-purpose digital logic products to achieve the levels of performance previously achieved only through custom design flows while maintaining efficient levels of power. These high performance levels are achieved at greatly reduced development costs and with lower risk of circuit problems as compared to the custom design flows used for desktop processors.
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