2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)最新文献_第4页

Time-gated CMOS SPAD and a Quantum Well Laser Diode with a CMOS Driver for Time-Resolved Diffuse Optics Imaging 时间门控CMOS SPAD和带CMOS驱动器的量子阱激光二极管用于时间分辨漫射光学成像

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573525

J. Nissinen, I. Nissinen, S. Jahromi, T. Talala, J. Kostamovaara

引用次数: 4

A Distributed DoS Detection Scheme for NoC-based MPSoCs 基于noc的mpsoc分布式DoS检测方案

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573524

C. G. Chaves, Siavoosh Payandeh Azad, T. Hollstein, Martha Johanna Sepúlveda

{"title":"A Distributed DoS Detection Scheme for NoC-based MPSoCs","authors":"C. G. Chaves, Siavoosh Payandeh Azad, T. Hollstein, Martha Johanna Sepúlveda","doi":"10.1109/NORCHIP.2018.8573524","DOIUrl":"https://doi.org/10.1109/NORCHIP.2018.8573524","url":null,"abstract":"The increasing threat of Denial of Service (DoS) attacks targeting Networks-on-Chip (NoC) based Multi-processors System-on-Chip (MPSoCs) imposes unprecedented challenges in terms of communication availability, especially for identifying the source of an attack in the NoC. Previous works show the possibility of executing DoS attacks on NoCs and propose mitigation methods that are deployed in all the NoC routers. However, this protection countermeasures usually impact the communication heavily. In order to achieve a better DoS protection, the point of attack should be identified. Towards this direction, in this paper, we propose a novel distributed DoS detection scheme being able to measure the performance degradation of sensitive flows and to detect the router where the attack enters the sensitive communication path. We perform an exploration regarding the effect of different types of attackers, where experimental work shows the best attack configuration parameters, and that a combination of two latency metrics can be leveraged not only for detecting a DoS attack, but also its interference point.","PeriodicalId":152077,"journal":{"name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131200813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Semiconductor Component Fault Assessment and Probability Impact Estimation on Application Level 半导体元件故障评估及应用层面的概率影响评估

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573501

Jonas Stricker, C. Kain, Jérôme Kirscher, Andi Buzo, L. Maurer, G. Pelz

{"title":"Semiconductor Component Fault Assessment and Probability Impact Estimation on Application Level","authors":"Jonas Stricker, C. Kain, Jérôme Kirscher, Andi Buzo, L. Maurer, G. Pelz","doi":"10.1109/NORCHIP.2018.8573501","DOIUrl":"https://doi.org/10.1109/NORCHIP.2018.8573501","url":null,"abstract":"Failures at component level can affect the application behavior in many different ways. During product development it is crucial to know the severity and the probability of such influence. The current methodologies for dealing with such problems are based on engineering judgment, but these are limited by the complexity of the applications and its components. In this paper, we present an automated approach in which we model the failures at component level, propagate them in application through simulation, cluster the failures and estimate the overall probability that different application failure modes have. This approach is applied on an automotive Electric Power Steering application while the components of interest are an analog-to-digital converter and a current sensor. The results show that the large number of failure modes on component level boils down to a very low number of application failure modes. For each of these failure modes the probability of occurrence is computed starting from the related root causes on component level1.","PeriodicalId":152077,"journal":{"name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121441622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Characterization and Considerations for Upset in FPGA FPGA中扰流特性及考虑因素

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573506

Christian Johansson, T. Manefjord

引用次数: 1

Low-Power Regulator for Micro Energy Harvesting Applications 微能量收集应用的低功率调节器

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573464

Tapani Nevalainen, E. Ferro, V. Brea, Paula López, A. Paasio

引用次数: 0

Low-latency Packet Parsing in Software Defined Networks 软件定义网络中的低延迟数据包解析

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573461

H. Zolfaghari, D. Rossi, J. Nurmi

引用次数: 6

Goal Formulation: Abstracting Dynamic Objectives for Efficient On-chip Resource Allocation 目标制定:为有效的片上资源分配抽象动态目标

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573451

Elham Shamsa, A. Kanduri, A. Rahmani, P. Liljeberg, A. Jantsch, N. Dutt

引用次数: 5

A 4.3-mW mm-Wave Divide-by-Two Circuit with 30% Locking Range in 28-nm FD-SOI CMOS 在28nm FD-SOI CMOS中，具有30%锁定范围的4.3 mw毫米波分二电路

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573468

Therese Forsberg, J. Wernehag, H. Sjöland, Markus Törmänen

引用次数: 0

Fault-Tolerant and Energy-Efficient Communication in Mixed-Criticality Networks-on-Chips 片上混合临界网络中的容错与高能效通信

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573469

Adele Maleki, Hamidreza Ahmadian, R. Obermaisser

{"title":"Fault-Tolerant and Energy-Efficient Communication in Mixed-Criticality Networks-on-Chips","authors":"Adele Maleki, Hamidreza Ahmadian, R. Obermaisser","doi":"10.1109/NORCHIP.2018.8573469","DOIUrl":"https://doi.org/10.1109/NORCHIP.2018.8573469","url":null,"abstract":"We observe a tremendous trend towards mixed-criticality systems, where subsystems of different safety assurance level coexist and interact. In addition, embedded systems are demanded to be efficient in terms of energy consumption to achieve longer operation time with the same battery capacity. This paper introduces a novel architecture for an adaptive time-triggered communication at the chip-level, which addresses the above challenges. In the proposed architecture, time-triggered communication offers safety by establishing temporal and spatial segregation of the communication channels. In addition, adaptivity enables the communication backbone to adapt the injection time of message according to the real execution time of computational tasks, thereby decreasing the overall makespan of the application and increasing the sleep time. In addition to power saving, adaptivity helps to achieve fault recovery, as a faulty subsystem can be shut down and replaced by a backup subsystem. The proposed concept has been evaluated by an example scenario. The results exhibit that using the proposed concept, makespan of the processor and consequently the energy consumption are reduced. In addition to energy, the amount of the used memory for storing the communication schedules is also decreased.","PeriodicalId":152077,"journal":{"name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"281 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116372270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Design of Stacked-MOS Transistor mm-Wave Class C Amplifiers for Doherty Power Amplifiers 用于Doherty功率放大器的堆叠mos晶体管毫米波C类放大器的设计

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573519

M. Montaseri, J. Aikio, T. Rahkonen, A. Pärssinen

引用次数: 1