Characterization and Considerations for Upset in FPGA

Abstract

The increase in performance and the relatively low cost have made the FPGA an attractive technology for use in various product areas. When used in safety-critical applications, the susceptibility against upsets due to cosmic radiation requires special considerations. In this paper, a number of mitigation techniques against upsets are discussed together with the use of a COTS IP. Furthermore, practical tests are performed to validate the upset rates and mitigation techniques. The tests are performed on a Xilinx UltraScale+MPSOC FPGA.