2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)最新文献

Flying-Capacitor Bottom-Plate Sampling Scheme for Low-Power High-Resolution SAR ADCs 低功耗高分辨率SAR adc的飞电容底板采样方案

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573458

Dmitry Osipov, S. Paul

引用次数: 4

A Low-Power Hardware Stack for Continuous Data Streaming from Telemetry Implants 一种用于遥测植入物连续数据流的低功耗硬件堆栈

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573522

Ilia Kempi, Nouman Ahmed, A. Hammer, Olaitan Olabode, Vishnu Unnikrishnan, M. Kosunen, J. Ryynänen

引用次数: 1

A 10b SAR ADC with Widely Scalable Sampling Rate and AGC Amplifier Front-End 具有广泛可扩展采样率和前端AGC放大器的10b SAR ADC

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573505

Ayca Akkaya, Firat Celik, A. Tajalli, Y. Leblebici

{"title":"A 10b SAR ADC with Widely Scalable Sampling Rate and AGC Amplifier Front-End","authors":"Ayca Akkaya, Firat Celik, A. Tajalli, Y. Leblebici","doi":"10.1109/NORCHIP.2018.8573505","DOIUrl":"https://doi.org/10.1109/NORCHIP.2018.8573505","url":null,"abstract":"This paper presents a low power successive approximation register (SAR) ADC and its front-end automatic gain control (AGC) amplifier designed in 65nm CMOS technology. Digitally controlled variable gain amplifier (VGA) in AGC loop is used to maximize the dynamic range. By adding the VGA front-end before the ADC, the dynamic range is improved by 20 dB and 48 dB SNDR is achieved for -40 dBV input signal. The VGA front-end also converts the single ended input signal into differential to be used in a differential SAR ADC design. VGA area is kept smaller by employing floating tunable high-value active resistors instead of passive resistors. The designed 10-bit SAR ADC can operate at a very wide range of sampling rates between 1 kS/s and 85 MS/s by changing the sampling duration from 1 to 3 clock cycles at the higher end of this sampling rate range. By using the programmable sampling duration technique, the maximum sampling rate of the ADC without compromising the SNDR performance is increased from 45 MS/s to 85 MS/s and around 10 dB improvement in SNDR is achieved at 85 MS/s sampling rate. The proposed analog front-end design including SAR ADC and AGC amplifier consumes 200 uW at 83.3 kS/s sampling rate and occupies 0.29mm2 area.","PeriodicalId":152077,"journal":{"name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116086791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

An 87% Peak Efficiency, 37W, Class H Audio Amplifier with GaN Output Stage 峰值效率87%，37W，带GaN输出级的H类音频放大器

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573508

Nardi Utomo, L. Siek, H. G. Yap, D. Disney, L. Selvaraj, Lulu Peng

引用次数: 1

Energy-Delay Trade-Offs in Instruction Register File Design 指令寄存器文件设计中的能量延迟权衡

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573504

Joonas Multanen, Heikki O. Kultala, P. Jääskeläinen

{"title":"Energy-Delay Trade-Offs in Instruction Register File Design","authors":"Joonas Multanen, Heikki O. Kultala, P. Jääskeläinen","doi":"10.1109/NORCHIP.2018.8573504","DOIUrl":"https://doi.org/10.1109/NORCHIP.2018.8573504","url":null,"abstract":"In order to decrease latency and energy consumption, processors use hierarchical memory systems to store temporally and spatially related instructions close to the core. Instruction register file (IRF) is an energy-efficient solution for the lowest level in the instruction memory hierarcy. Being compiler-controlled, it removes the area and energy overheads involved in cache tag checking and adds flexibility in the separation of the instruction fetch and execution. In this paper, we systematically evaluate for the first time the effect of three IRF design variations on energy and delay against an unoptimized baseline IRF. Having instruction fetch and decode with IRF in the same pipeline stage allows minimal delay branching, but results in low operating clock frequency and impaired energy delay product compared to splitting them into two stages. Assuring instruction presence in IRF before execution with software reduces the area and increases maximum clock frequency compared to assurance with hardware, but requires compiler analysis. With a proposed compiler-analyzed instruction placement and co-designed hardware implementation, energy consumption with the best IRF variant is reduced by 9% on average with EEMBC Coremark and CHStone benchmaks. The energy delay product is improved by 23% when compared to the baseline IRF approach.","PeriodicalId":152077,"journal":{"name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116615143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Unleashing the full power of feed-forward opamps: a 200MHz, fully differential, conditionally stable, 36dB gain PGA, using a four-stage multi-path 2.5V amplifier with double feed-forward compensation. 释放前馈放大器的全部功率:200MHz，全差分，条件稳定，36dB增益的PGA，使用带双前馈补偿的四级多径2.5V放大器。

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573502

V. Kampus, Martin Trojer, Robert Teschner

引用次数: 1

Comparison of Ultra Low Power Full Adder Cells in 22 nm FDSOI Technology 超低功耗全加法器电池在22 nm FDSOI技术中的比较

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573516

S. H. Zadeh, T. Ytterdal, S. Aunet

引用次数: 2

Time-Predictable Distributed Shared Memory for Multi-Core Processors 多核处理器的时间可预测分布式共享内存

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573463

Morten B. Petersen, Anthon V. Riber, S. T. Andersen, Martin Schoeberl

引用次数: 1

Implementation of an Area Efficient Crypto Processor for a NB-IoT SoC Platform 面向NB-IoT SoC平台的区域高效加密处理器的实现

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573517

Luis Cavo, S. Fuhrmann, Liang Liu

引用次数: 1

A Design Approach for SiGe Low-Noise Amplifiers Using Wideband Input Matching 基于宽带输入匹配的SiGe低噪声放大器设计方法

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573488

Zhe Chen, Hao Gao, P. Baltus

引用次数: 2