Comparison of Ultra Low Power Full Adder Cells in 22 nm FDSOI Technology

Abstract

Five ultra low voltage and low power full adders have been designed and analyzed with CMOS logic structure. To compare these adders, different metrics including worst case delay, average power, PDP, and PDP*Leakage have been investigated in the supply voltage varying from 140-160 mV. All the full adders have been designed and verified with Cadence Virtuoso design in a commercially available 22 nm FDSOI technology. An extended body bias voltages introduced in a 22 nm FDSOI technology have been used to balance Pull Up/Pull Down Networks and have a high functional yield. The test bench has been used to verify the functionality of full adders automatically in different conditions of temperature and supply voltage. The simulation results show that an Xor based adder is the best of all having the lowest delay, power, PDP, and PDP*Leakage in different conditions.