发布求助
文献互助 智能选刊 最新文献

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)最新文献

筛选
英文 中文
Three-Dimensional Dynamic Programming Accelerator for Multiple Sequence Alignment 多序列比对三维动态规划加速器
2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573523
Ruei-Ting Chien, Yi-Lun Liao, Chien-An Wang, Yu-Cheng Li, Yi-Chang Lu
{"title":"Three-Dimensional Dynamic Programming Accelerator for Multiple Sequence Alignment","authors":"Ruei-Ting Chien, Yi-Lun Liao, Chien-An Wang, Yu-Cheng Li, Yi-Chang Lu","doi":"10.1109/NORCHIP.2018.8573523","DOIUrl":"https://doi.org/10.1109/NORCHIP.2018.8573523","url":null,"abstract":"Three sequence alignment can be used to improve the accuracy of multiple sequence alignment in genomics. In this paper, we design a hardware accelerator for three-dimensional dynamic programming algorithm of three sequence alignment. By utilizing parallel processing elements, our design can find the optimal alignment scores in a shorter time than that required by software. In addition, we propose a memory-efficient slicing method for three-dimensional dynamic programming in order to process sequences of longer lengths. The hardware accelerator is implemented on both FPGA and ASIC. The ASIC implementation using TSMC 40nm technology can achieve at least 160× speedup over the software implementation.","PeriodicalId":152077,"journal":{"name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127014005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Master-Clone Placement with Individual Clock Tree Implementation – a Case on Physical Chip Design 具有单个时钟树实现的主克隆放置-物理芯片设计的一个案例
2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573453
O. Schrape, A. Balashov, A. Simevski, Carlos Benito, M. Krstic
{"title":"Master-Clone Placement with Individual Clock Tree Implementation – a Case on Physical Chip Design","authors":"O. Schrape, A. Balashov, A. Simevski, Carlos Benito, M. Krstic","doi":"10.1109/NORCHIP.2018.8573453","DOIUrl":"https://doi.org/10.1109/NORCHIP.2018.8573453","url":null,"abstract":"A hybrid design approach of the hierarchical physical implementation design flow is presented and demonstrated on a fault-tolerant low-power multiprocessor system. The proposed flow allows to implement selected submodules in parallel with contrary requirements such as identical placement and individual block implementation. The overall system contains four Leon2 cores and communicates via the Waterbear framework and supports Adaptive Voltage Scaling (AVS) functionality. Three of the processor core variants are derived from the first baseline reference core but implemented individually at block level based on their clock tree specification. The chip is prepared for space applications and designed with triple modular redundancy (TMR) for control parts. The low-power performance is enabled by contemporary power and clock management control. An ASIC is fabricated in a low-power $0.13 mu mathrm{m}$ BiCMOS technology process node.","PeriodicalId":152077,"journal":{"name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126875064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信