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2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)最新文献

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A Radiation Hardened 16 GS/s Arbitrary Waveform Generator IC for a Submillimeter Wave Chirp-Transform Spectrometer 用于亚毫米波啁啾变换光谱仪的抗辐射16gs /s任意波形发生器集成电路
2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573493
P. Ostrovsky, O. Schrape, K. Tittelbach-Helmrich, F. Herzel, G. Fischer, D. Hellmann, P. Borner, A. Loose, P. Hartogh, D. Kissinger
{"title":"A Radiation Hardened 16 GS/s Arbitrary Waveform Generator IC for a Submillimeter Wave Chirp-Transform Spectrometer","authors":"P. Ostrovsky, O. Schrape, K. Tittelbach-Helmrich, F. Herzel, G. Fischer, D. Hellmann, P. Borner, A. Loose, P. Hartogh, D. Kissinger","doi":"10.1109/NORCHIP.2018.8573493","DOIUrl":"https://doi.org/10.1109/NORCHIP.2018.8573493","url":null,"abstract":"This paper describes a radiation hardening design approach of a dual channel 16 GSps single chip arbitrary waveform generator (AWG) – a complex mixed-signal ASIC – that consists of a low phase noise 16 GHz PLL, two 1.6 Mbit SRAM blocks, two multiplexing chains, and two 4-bit DACs. The ASIC is dedicated to be a part of a submillimeter wave spectrometer that shall operate in deep-space environment. Under stringent power budget conditions, a selective radiation protection of the ASIC has been applied. The arbitrary waveform generator has been fabricated in a 130 nm SiGe BiCMOS process. Correct functionality has been verified in lab and will be further tested in an irradiation facility.","PeriodicalId":152077,"journal":{"name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127240636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Application Specific Integrated Gate-Drive Circuit for Driving Self-Oscillating Gallium Nitride & Logic-Level Power Transistors 用于驱动自振荡氮化镓及逻辑级功率晶体管的专用集成门驱动电路
2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573497
Jacob E. F. Overgaard, J. C. Hertel, J. Pejtersen, A. Knott
{"title":"Application Specific Integrated Gate-Drive Circuit for Driving Self-Oscillating Gallium Nitride & Logic-Level Power Transistors","authors":"Jacob E. F. Overgaard, J. C. Hertel, J. Pejtersen, A. Knott","doi":"10.1109/NORCHIP.2018.8573497","DOIUrl":"https://doi.org/10.1109/NORCHIP.2018.8573497","url":null,"abstract":"Wide bandgap power semiconductors are key enablers for increasing the power density of switch-mode power supplies. However, they require new gate drive technologies. This paper examines and characterizes a fabricated gate-driver in a class-E resonant inverter. The gate-driver’s total area of 1.2mm2 includes two high-voltage transistors for gate-driving, integrated complementary metal-oxide-semiconductor (CMOS) gate-drivers, high-speed floating level-shifter and reset circuitry. A prototype printed circuit board (PCB) was designed to assess the implications of an electrostatic discharge (ESD) diode, its parasitic capacitance and package bondwire connections. The parasitic capacitance was estimated using its discharge time from an initial voltage and the capacitance is 56.7 pF. Both bondwires and the diode’s parasitic capacitance is neglegible. The gate-driver’s functional behaviour is validated using a parallel LC resonant tank resembling a self-oscillating gate-drive. Measurements and simulations show the ESD diode clamps the output voltage to a minimum of –2V.","PeriodicalId":152077,"journal":{"name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"79 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128113424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
FPGA Based Hybrid Computing Platform for ESS Linac Simulator 基于FPGA的ESS直线模拟器混合计算平台
2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573518
A. Jeevaraj, E. Laface, Maurizio Donna, F. Edman, Liang Liu
{"title":"FPGA Based Hybrid Computing Platform for ESS Linac Simulator","authors":"A. Jeevaraj, E. Laface, Maurizio Donna, F. Edman, Liang Liu","doi":"10.1109/NORCHIP.2018.8573518","DOIUrl":"https://doi.org/10.1109/NORCHIP.2018.8573518","url":null,"abstract":"This paper presents a scalable and high-throughput hybrid computing platform for the real-time multi-particle based Linac (Linear accelerator) simulation model to be used at the European Spallation Source (ESS). The multi-particle simulation model with non-linear modeling is needed to provide a realistic behavior of the particle beam for reducing the losses at the superconducting structures. The computation complexity of the simulations can reach 1012 matrix multiplication operations for a test case of 106 beam particles simulated over 106 cells. An OpenCL (Open Computing Language) based framework is used to map the processing intensive parts of the simulation model efficiently to any configuration of a CPU-, GPU- and FPGA-based platform. Optimizations using data precision strategies have also been explored to further improve the throughput after reaching memory access saturation. We are able to achieve up to $89 times$ speed up compared to a C++ benchmark of the same system.","PeriodicalId":152077,"journal":{"name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114121256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
VELS: VHDL E-Learning System for Automatic Generation and Evaluation of Per-Student Randomized Assignments 用于自动生成和评估每个学生随机作业的VHDL电子学习系统
2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573455
Martin Mosbeck, Daniel Hauer, A. Jantsch
{"title":"VELS: VHDL E-Learning System for Automatic Generation and Evaluation of Per-Student Randomized Assignments","authors":"Martin Mosbeck, Daniel Hauer, A. Jantsch","doi":"10.1109/NORCHIP.2018.8573455","DOIUrl":"https://doi.org/10.1109/NORCHIP.2018.8573455","url":null,"abstract":"Learning digital design with VHDL requires extensive practice with solving many assignments independently, which is difficult to provide in a university setting with high student-teacher ratio. Automated assessment systems can help by facilitating a flexible, satisfying learning environment for students. This paper describes the VHDL E-learning system VELS, its implementation, and our experience over the last three years with approximately 1000 students. VELS is a flexible system with key features including a uniform task system with parameterized tasks, non-static testbenches, communication over email, a tool that aids in creating new tasks, flexible configuration possibilities with different course modes, exchangeable simulator backend and multi language support.","PeriodicalId":152077,"journal":{"name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123871193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
High-speed Sampling System in CMOS CMOS高速采样系统
2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573459
E. Ulvestad, K. G. Kjelgård, T. M. Khanshan, D. Wisland, T. Lande
{"title":"High-speed Sampling System in CMOS","authors":"E. Ulvestad, K. G. Kjelgård, T. M. Khanshan, D. Wisland, T. Lande","doi":"10.1109/NORCHIP.2018.8573459","DOIUrl":"https://doi.org/10.1109/NORCHIP.2018.8573459","url":null,"abstract":"In this paper we will present a high-speed sampling system intended for use in a depth selective or depth resolved spectroscopic LIDAR for transcutanuous blood assessment. A continuous-time (CT) sampling solution enabling sampling rates close to 100 GHz, close to two orders of magnitude faster than standard clocked systems. Based on experimental verification in 90nm CMOS technology, opportunities and limitations of CT sampling systems are analyzed.","PeriodicalId":152077,"journal":{"name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116266829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 24GHz, 18dBm, Broadband, Three Stacked Power Amplifier in 28nm FDSOI 24GHz, 18dBm，宽带，28nm FDSOI三堆叠功率放大器
2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573450
I. Din, S. Andersson, Therese Forsberg, H. Sjöland
{"title":"A 24GHz, 18dBm, Broadband, Three Stacked Power Amplifier in 28nm FDSOI","authors":"I. Din, S. Andersson, Therese Forsberg, H. Sjöland","doi":"10.1109/NORCHIP.2018.8573450","DOIUrl":"https://doi.org/10.1109/NORCHIP.2018.8573450","url":null,"abstract":"A three stacked power amplifier implemented in 28nm fully depleted silicon-on-insulator complementary metal oxide semi-conductor technology (FDSOI CMOS) is presented. It has a differential architecture with on-chip input and output transformer baluns. The PA achieves a saturated output power level of 17.9dBm with a peak power added efficiency of 7% and an output referred gain compression point of 16.2dBm. It occupies a silicon area of 0.4$mm^{2}$, uses a supply voltage of 3V, and has a 3.3GHz 1-dB bandwidth at 24GHz.","PeriodicalId":152077,"journal":{"name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121154347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Dynamically Reconfigurable Gearbox Switched-Capacitor DC-DC Converter 动态可重构变速箱开关电容DC-DC转换器
2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573520
D. Larsen, M. Vinter, I. Jørgensen
{"title":"Dynamically Reconfigurable Gearbox Switched-Capacitor DC-DC Converter","authors":"D. Larsen, M. Vinter, I. Jørgensen","doi":"10.1109/NORCHIP.2018.8573520","DOIUrl":"https://doi.org/10.1109/NORCHIP.2018.8573520","url":null,"abstract":"A dual output battery-connected reconfigurable switched capacitor dc-dc converter (SCC) is presented. The design improves the overall power efficiency of the system by reconfiguring the SCC output stage based on the output load scenario. The number of capacitors to use in an SCC is a tradeoff between area and efficiency. Having more capacitors improves efficiency but increases the implementation area and cost. The proposed combined dynamically reconfigurable output stage changes the number of capacitors used for each output depending on the load. The implemented converter is compared with a solution where an SCC is implemented separately for each of the outputs. Transistor level simulations of the proposed and prior art output stages show an overall improved efficiency.","PeriodicalId":152077,"journal":{"name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131573589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Insertion-Loss Optimization of Transformer-based Matching Networks for mm-Wave Applications 毫米波应用中基于变压器匹配网络的插入损耗优化
2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573510
David Bierbuesse, R. Negra
{"title":"Insertion-Loss Optimization of Transformer-based Matching Networks for mm-Wave Applications","authors":"David Bierbuesse, R. Negra","doi":"10.1109/NORCHIP.2018.8573510","DOIUrl":"https://doi.org/10.1109/NORCHIP.2018.8573510","url":null,"abstract":"A new design methodology for insertion-loss (IL) optimization of transformer-based input matching networks is presented in this paper. With respect to a particular load impedance, the optimum transformer (TF) specifications, i.e. primary and secondary inductance $L_{p}$ and $L_{s}$ and the coupling factor $k$, can be determined. As a design example, this approach is presented for an integrated planar TF topology in a 65 nm CMOS process. It is verified by EM co-simulations in ADS Momentum at a centre frequency of 60 GHz.","PeriodicalId":152077,"journal":{"name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"15 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128805720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis and Design of ESD Protection for Robust Low-Power Pierce Crystal Oscillator Startup 小功率穿孔晶振稳健启动ESD防护分析与设计
2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573499
K. B. Ostman, Erlend Strandvik, P. Corbishley, T. Vedal, Mika Salmi
{"title":"Analysis and Design of ESD Protection for Robust Low-Power Pierce Crystal Oscillator Startup","authors":"K. B. Ostman, Erlend Strandvik, P. Corbishley, T. Vedal, Mika Salmi","doi":"10.1109/NORCHIP.2018.8573499","DOIUrl":"https://doi.org/10.1109/NORCHIP.2018.8573499","url":null,"abstract":"Integrated CMOS crystal oscillators (XO) access the off-chip crystal through interfaces that require electrostatic discharge (ESD) protection circuitry. The properties of this circuitry have a significant impact on the available negative resistance and startup conditions of the oscillator, especially if ultra-low-power operation is desired. This paper uses small-signal, root locus and impedance locus analyses to obtain guidelines for ESD circuit dimensioning, balancing the simultaneous need for low power, sufficient ESD tolerance, and robust startup. The approach thus eliminates the need for time-consuming simulation searches that cover the vast design and fabrication corner space for a circuit with slow startup, providing instead a reliable approximation as input for detailed design. A current-starved 32-MHz complementary Pierce XO is used as an example.","PeriodicalId":152077,"journal":{"name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133472802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On Designing PUF-Based TRNGs with Known Answer Tests 基于已知答案测试puf的trng设计
2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573489
Yang Yu, E. Dubrova, M. Näslund, S. Tao
{"title":"On Designing PUF-Based TRNGs with Known Answer Tests","authors":"Yang Yu, E. Dubrova, M. Näslund, S. Tao","doi":"10.1109/NORCHIP.2018.8573489","DOIUrl":"https://doi.org/10.1109/NORCHIP.2018.8573489","url":null,"abstract":"Random numbers are widely used in cryptographic algorithms and protocols. A faulty true random number generator (TRNG) may open a door into a system in spite of cryptographic protection. It is therefore important to design TRNGs so that they can be tested at different stages of their lifetime to assure their trustworthiness. In this paper, we propose a method for designing physical unclonable function (PUF)-based TRNGs which can be tested in-field by known answer tests. We present a prototype FPGA implementation of the proposed TRNG based on an arbiter PUF which passes all NIST 800-22 statistical tests and has the minimal entropy of 0.918 estimated according to NIST 800-90B recommendations. This is a nontrivial achievement given that arbiter PUFs are notoriously hard to place in a symmetric manner in FPGAs.","PeriodicalId":152077,"journal":{"name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116701818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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