Analysis and Design of ESD Protection for Robust Low-Power Pierce Crystal Oscillator Startup

Abstract

Integrated CMOS crystal oscillators (XO) access the off-chip crystal through interfaces that require electrostatic discharge (ESD) protection circuitry. The properties of this circuitry have a significant impact on the available negative resistance and startup conditions of the oscillator, especially if ultra-low-power operation is desired. This paper uses small-signal, root locus and impedance locus analyses to obtain guidelines for ESD circuit dimensioning, balancing the simultaneous need for low power, sufficient ESD tolerance, and robust startup. The approach thus eliminates the need for time-consuming simulation searches that cover the vast design and fabrication corner space for a circuit with slow startup, providing instead a reliable approximation as input for detailed design. A current-starved 32-MHz complementary Pierce XO is used as an example.