多序列比对三维动态规划加速器

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI:10.1109/NORCHIP.2018.8573523

Ruei-Ting Chien, Yi-Lun Liao, Chien-An Wang, Yu-Cheng Li, Yi-Chang Lu

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引用次数: 2

摘要

三序列比对可以提高基因组学中多序列比对的准确性。在本文中，我们设计了一个硬件加速器，用于三序列对齐的三维动态规划算法。利用并行处理元素，我们的设计可以在比软件所需时间更短的时间内找到最优对齐分数。此外，我们提出了一种存储效率高的三维动态规划切片方法，以处理更长的序列。硬件加速器是在FPGA和ASIC上实现的。采用台积电40nm技术的ASIC实现可以实现比软件实现至少160倍的加速。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Three-Dimensional Dynamic Programming Accelerator for Multiple Sequence Alignment

Three sequence alignment can be used to improve the accuracy of multiple sequence alignment in genomics. In this paper, we design a hardware accelerator for three-dimensional dynamic programming algorithm of three sequence alignment. By utilizing parallel processing elements, our design can find the optimal alignment scores in a shorter time than that required by software. In addition, we propose a memory-efficient slicing method for three-dimensional dynamic programming in order to process sequences of longer lengths. The hardware accelerator is implemented on both FPGA and ASIC. The ASIC implementation using TSMC 40nm technology can achieve at least 160× speedup over the software implementation.

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来源期刊

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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