Flying-Capacitor Bottom-Plate Sampling Scheme for Low-Power High-Resolution SAR ADCs

Abstract

A new sampling scheme for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed in this paper. The switching scheme eliminates two major problems of traditional SAR ADC architectures: first, the high energy demand of the input driver, because of high input capacitance; and second, the trade-off between linearity and, consequently, bottom-plate sampling, and area savings and, consequently, upper-plate sampling. The proposed sampling scheme allows reduction of the sampling capacitance to a single unit capacitor and the use of high linear bottom-plate sampling without sacrificing the double area on digital-to-analog converter (DAC). This method works with most previously published switching schemes.