2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)最新文献_第2页

CMOS photosensors for LIDAR 用于激光雷达的CMOS光传感器

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573471

T. M. Khanshan, K. G. Kjeldgard, E. Ulvestad, D. Wisland, T. Lande

引用次数: 0

Design and Implementation of Multi-Purpose DCT/DST-Specific Accelerator on Heterogeneous Multicore Architecture 在异构多核架构上设计和实现多用途 DCT/DST 特定加速器

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573457

Sajjad Nouri, R. G. Youvalari, J. Nurmi

{"title":"Design and Implementation of Multi-Purpose DCT/DST-Specific Accelerator on Heterogeneous Multicore Architecture","authors":"Sajjad Nouri, R. G. Youvalari, J. Nurmi","doi":"10.1109/NORCHIP.2018.8573457","DOIUrl":"https://doi.org/10.1109/NORCHIP.2018.8573457","url":null,"abstract":"This paper presents the implementation of various sizes of Discrete Cosine transform (DCT) and Discrete Sine Transform (DST) dedicated for High Efficiency Video Coding (HEVC) standard by using template-based Coarse-Grained Reconfigurable Arrays (CGRAs) as accelerators on Heterogeneous Accelerator-Rich Platform (HARP). The proposal makes multipurpose DCT/DST specific accelerators in such a way that final architecture consists of 4/8/16/32–point DCT and 4-point DST. The accelerators are primarily designed by crafting template-based CGRA devices at different dimensions and then arranging them on a Network-on-Chip platform along with a few RISC cores. In this research work, the performance of each DCT/DST-specific accelerator, the collective performance of the whole platform and the NoC traffic are recorded in terms of the number of clock cycles and several high-level performance metrics. Conducted experiments show that 4-point DCT and 4-point DST can be implemented completely in 54 and 56 clock cycles, respectively, while for 8/16/32–point DCT, 67, 179 and 354 clock cycles are required, respectively. The achieved total power dissipation and energy consumption based on post placement and routing information are equal to 4.1 W and $10.87~mu {mathrm {J}}$, respectively with 256 instantiated Processing Elements (PEs) at 200.0 MHz operating frequency. It resulted to a performance of 51.2 Giga Operations Per Second (GOPS) and 12 MOPS/mW as an architectural constant for the HARP template on 28 nm Altera Stratix-V chip. The proposed architecture is able to sustain Full HD 1080p format at 30 fps on FPGA.","PeriodicalId":152077,"journal":{"name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125781923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Multi-Swarm based NoC Configuration and Synthesis 基于多群的NoC配置与合成

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573462

Muhammad Obaidullah, G. Khan, Fei Yuan

引用次数: 2

A Row-Column Accessed Dynamic Element Matching DAC Architecture for SAR ADCs SAR adc的行-列访问动态元件匹配DAC体系结构

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573513

Mustafa Kilic, Selman Ergünay, Y. Leblebici

引用次数: 1

Design of Multi-Stacked CMOS mm-Wave Power Amplifiers for Phased Array Applications Using Triple-Well Process 基于三阱工艺的相控阵多堆叠CMOS毫米波功率放大器设计

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573452

M. Montaseri, R. Vuohtoniemi, J. Aikio, T. Rahkonen, A. Pärssinen

引用次数: 2

A Configurable Hysteresis Comparator for Asynchronous Sigma-Delta Modulators 异步Sigma-Delta调制器的可配置迟滞比较器

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573454

Olaitan Olabode, Vishnu Unnikrishnan, Ilia Kempi, A. Hammer, M. Kosunen, J. Ryynänen

引用次数: 0

Building Lumped Models for Measured Passive mm-wave Components 为测量无源毫米波分量建立集总模型

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573484

E. Sankila, Veeti Kiuru, J. Aikio, T. Rahkonen

引用次数: 0

Design Considerations and Evaluation of a High-Speed SAR ADC 高速SAR ADC的设计考虑与评估

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573500

Victor Åberg, C. Fager, L. Svensson

引用次数: 0

GPU-enhanced Multimodal Dense Matching gpu增强的多模态密集匹配

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573526

Nicolai Behmann, M. Mehltretter, S. Kleinschmidt, Bernardo Wagner, C. Heipke, H. Blume

引用次数: 1

Analysis of Synchronous-Asynchronous NoC for the Dark Silicon Era 暗硅时代同步-异步NoC分析

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573470

Reem W. Etman, Salma Hesham, Klaus Hoffman, M. A. E. Ghany, D. Göhringer

{"title":"Analysis of Synchronous-Asynchronous NoC for the Dark Silicon Era","authors":"Reem W. Etman, Salma Hesham, Klaus Hoffman, M. A. E. Ghany, D. Göhringer","doi":"10.1109/NORCHIP.2018.8573470","DOIUrl":"https://doi.org/10.1109/NORCHIP.2018.8573470","url":null,"abstract":"Future chips are anticipated to feature hundreds of on-die resources, but a significant portion of silicon area in these chips will be powered-off or “dark”. As a result, only a limited number of cores of future processors can be powered on simultaneously. In this paper, a novel NoC architecture is proposed, called Dark Silicon Synchronous-Asynchronous (DSSA) NoC, that offer a promising solution from the latency perspective in consideration to the number of hops from source to destination. In this design two layers of architecturally analogous synchronous and asynchronous TDM routers are integrated, leveraging the extra transistors available due to dark silicon for a hard real-time multiprocessor platform. At a given time, at most, only one of the network layers is illuminated while the other is dark. Layer selection performed at the granularity of router port with applied power gating technique uniquely in a source routed TDM router. To verify the design, a$4times4$ bitorus synchronous, asynchronous and DSSA NoCs are implemented in 90-nm CMOS technology and the results are compared in the fields of area, speed, latency and power consumption, which shows improved message latency by DSSA NoC. The results further show the effects of the power gating technique to the TDM NoC, which offers up to 50% power savings in comparison to the conventional synchronous and asynchronous TDM NoCs. This illustrates DSSA as an improved latency NoC solution in future dark silicon chips.","PeriodicalId":152077,"journal":{"name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124354779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2