2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)最新文献_第3页

Towards Multidimensional Verification: Where Functional Meets Non-Functional 走向多维验证:功能与非功能的相遇

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573495

M. Jenihhin, X. Lai, Tara Ghasempouri, J. Raik

引用次数: 7

An Embedded Programmable Processor for Compressive Sensing Applications 一种用于压缩感知应用的嵌入式可编程处理器

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573494

Mehdi Safarpour, Ilkka Hautala, O. Silvén

引用次数: 3

Design and Implementation of 2D IDCT/IDST-Specific Accelerator on Heterogeneous Multicore Architecture 异构多核架构下二维IDCT/ idst专用加速器的设计与实现

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573492

Mohammad Ali Pourabed, Sajjad Nouri, J. Nurmi

{"title":"Design and Implementation of 2D IDCT/IDST-Specific Accelerator on Heterogeneous Multicore Architecture","authors":"Mohammad Ali Pourabed, Sajjad Nouri, J. Nurmi","doi":"10.1109/NORCHIP.2018.8573492","DOIUrl":"https://doi.org/10.1109/NORCHIP.2018.8573492","url":null,"abstract":"The paper talks about how to implement different sizes of Inverse Discrete Cosine Transform (IDCT) as well as Inverse Discrete Sine transform (IDST) that are dedicated on High Efficiency Video Coding (HEVC) standard through employing Coarse-Grained Reconfigurable Arrays (CGRAs) as a template-based accelerators on Heterogeneous Accelerator-Rich Platform (HARP). The proposal designs multi-purpose IDCT/IDST-based accelerators in a manner that the final architecture is made up of 4-point IDST and 4/8-point IDCT. The designing of the accelerators is done by creating template-based CGRA devices at various dimensions after which they are arranged in a sequential manner over a structure that is Network-on-Chip(NoC) based accompanied by a number of RISC cores. The research records the IDCT/IDST-specific accelerator performance, the entire platform’s performance, as well as the traffic of the NoC with regard to the total number of clock cycles made as well as several other high-level metrics of performance. The experiments that were conducted found that 4-point IDCT and 4-point IDST can be totally implemented in 56 clock cycles. For 8-point IDCT, the clock cycles required are 64. The total power dissipation, as well as energy consumption centred on information on routing and post placement, are all equal to 4.03 mW and 1.76 $mu J$ for 4- point IDCT/IDST and 3.06 $mu J$ for 8-point IDCT, respectively. Furthermore, the use of 256 instantiated Processing Elements (PEs) at an operating frequency of 200.0 MHz results to a 51.2 Giga Operations Per Second (GOPS) performance and 0.012 GOPS/mW architectural constant for the HARP model on the 28 nm Altera Stratix-V chip. The architecture under the proposal is capable of fully sustaining a format of Full HD 1080P at 30 fps on FPGA.","PeriodicalId":152077,"journal":{"name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114754928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 15-50GHz Multiplexer Circuit in 130nm SiGe BiCMOS Technology for Ultra-Wide Frequency Ramps in FMCW Radar 基于130nm SiGe BiCMOS技术的15-50GHz多路复用电路用于FMCW雷达的超宽频率坡道

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573467

F. Herzel, A. Ergintav, J. Borngräber, D. Kissinger

引用次数: 1

A RF Pulse-Width and Pulse-Position Modulator IC in 28 nm FDSOI CMOS 一种28nm FDSOI CMOS射频脉宽和脉位调制器集成电路

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573465

M. Grozing, J. Digel, Thomas Veigel, R. Bieg, Jianxiong Zhang, Simon Brandl, Martin Schmidt, C. Haslach, Daniel Markert, W. Templ

引用次数: 9

Noise Considerations in Pulse-Shaping Based TIA Channel Designed for a Pulsed TOF Laser Radar Receiver 脉冲TOF激光雷达接收机基于脉冲整形TIA通道的噪声考虑

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573466

Aram Baharmast, J. Kostamovaara

引用次数: 5

A Comparison of Polar and Quadrature RF-PWM 极性和正交RF-PWM的比较

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573456

Muhammad Fahim Ul Haque, Muhammad Touqir Pasha, Tahir Malik, T. Johansson

引用次数: 0

Current Readout Circuit for Point-of-Care Infectious Disease Diagnostics in Animal Health 动物健康中即时传染病诊断的电流读出电路

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573507

Kathy Hanley, Aidan Murphy, Niamh Creedon, A. O’Riordan, Daniel O’Hare, I. O'Connell

引用次数: 2

Power Intent from Initial ESL Prototypes: Extracting Power Management Parameters* 从初始ESL原型的电源意图:提取电源管理参数*

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573511

David Lemma, Mehran Goli, Daniel Große, R. Drechsler

{"title":"Power Intent from Initial ESL Prototypes: Extracting Power Management Parameters*","authors":"David Lemma, Mehran Goli, Daniel Große, R. Drechsler","doi":"10.1109/NORCHIP.2018.8573511","DOIUrl":"https://doi.org/10.1109/NORCHIP.2018.8573511","url":null,"abstract":"The increase in digital circuit complexity not only stems from sophisticated functionality, but also from power concerns. Power concerns are addressed via the realization of power intent (the specification for power). Unlike functional specifications, power intent is generally implicit within an initial ESL Prototype. For power intent to become explicit, it needs to be expressed in terms of Power Management parameters. These parameters are major indicators of the efforts involved in realizing the power intent. We introduce an automated method to extract two Power Management parameters (number of Control Signals and Power Modes) from ESL prototypes. These parameters are extracted in a two-step process. First, relevant structural and behavioral information of the prototype is retrieved and translated into an activity profile. Following this, an analysis is performed on the activity profile to extract the power management parameters. The effectiveness and efficiency of the method is demonstrated by its application on several ESL benchmarks.","PeriodicalId":152077,"journal":{"name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132037571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A 0.0186 mm2, 0.65 V Supply, 9.53 ps RMS Jitter All-Digital PLL for Medical Implants 一个0.0186 mm2, 0.65 V电源，9.53 ps RMS抖动全数字锁相环，用于医疗植入物

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI: 10.1109/NORCHIP.2018.8573491

A. R. Palaniappan, L. Siek

引用次数: 3