基于130nm SiGe BiCMOS技术的15-50GHz多路复用电路用于FMCW雷达的超宽频率坡道

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI:10.1109/NORCHIP.2018.8573467

F. Herzel, A. Ergintav, J. Borngräber, D. Kissinger

{"title":"基于130nm SiGe BiCMOS技术的15-50GHz多路复用电路用于FMCW雷达的超宽频率坡道","authors":"F. Herzel, A. Ergintav, J. Borngräber, D. Kissinger","doi":"10.1109/NORCHIP.2018.8573467","DOIUrl":null,"url":null,"abstract":"We present a high-speed 2:1 multiplexer for ultra-wideband phase-locked loops (PLL) to be used in FMCW radar systems. The circuit works up to frequencies of 50GHz and allows an instantaneous switching between the outputs of two PLLs. At 30GHz, the measured added phase noise of the MUX is −129.6 dBc/Hz at 1MHz offset, and the input isolation at 30GHz is better than 36dB. The core multiplexer circuit excluding buffers occupies a chip area of 0.03mm2 and draws 22m A from a 3V supply. The whole test chip including input buffers, output buffers and bondpads occupies a chip area of 0.4mm2 and draws 95 mA from 3V. An array of two PLLs with overlapping tuning ranges using this multiplexer is proposed for high-resolution, high-precision FMCW radar.","PeriodicalId":152077,"journal":{"name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 15-50GHz Multiplexer Circuit in 130nm SiGe BiCMOS Technology for Ultra-Wide Frequency Ramps in FMCW Radar\",\"authors\":\"F. Herzel, A. Ergintav, J. Borngräber, D. Kissinger\",\"doi\":\"10.1109/NORCHIP.2018.8573467\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a high-speed 2:1 multiplexer for ultra-wideband phase-locked loops (PLL) to be used in FMCW radar systems. The circuit works up to frequencies of 50GHz and allows an instantaneous switching between the outputs of two PLLs. At 30GHz, the measured added phase noise of the MUX is −129.6 dBc/Hz at 1MHz offset, and the input isolation at 30GHz is better than 36dB. The core multiplexer circuit excluding buffers occupies a chip area of 0.03mm2 and draws 22m A from a 3V supply. The whole test chip including input buffers, output buffers and bondpads occupies a chip area of 0.4mm2 and draws 95 mA from 3V. An array of two PLLs with overlapping tuning ranges using this multiplexer is proposed for high-resolution, high-precision FMCW radar.\",\"PeriodicalId\":152077,\"journal\":{\"name\":\"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)\",\"volume\":\"71 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NORCHIP.2018.8573467\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NORCHIP.2018.8573467","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

我们提出了一种用于超宽带锁相环(PLL)的高速2:1多路复用器，用于FMCW雷达系统。该电路工作频率高达50GHz，并允许两个锁相环输出之间的瞬时切换。在30GHz时，测量到的MUX在1MHz偏置时的附加相位噪声为- 129.6 dBc/Hz，在30GHz时的输入隔离优于36dB。除去缓冲器的核心多路复用器电路占用了0.03mm2的芯片面积，并从3V电源中吸取22m a。整个测试芯片包括输入缓冲器、输出缓冲器和键垫，芯片面积为0.4mm2，从3V输出95ma。在高分辨率、高精度FMCW雷达中，提出了一种具有重叠调谐范围的两个锁相环阵列。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A 15-50GHz Multiplexer Circuit in 130nm SiGe BiCMOS Technology for Ultra-Wide Frequency Ramps in FMCW Radar

We present a high-speed 2:1 multiplexer for ultra-wideband phase-locked loops (PLL) to be used in FMCW radar systems. The circuit works up to frequencies of 50GHz and allows an instantaneous switching between the outputs of two PLLs. At 30GHz, the measured added phase noise of the MUX is −129.6 dBc/Hz at 1MHz offset, and the input isolation at 30GHz is better than 36dB. The core multiplexer circuit excluding buffers occupies a chip area of 0.03mm2 and draws 22m A from a 3V supply. The whole test chip including input buffers, output buffers and bondpads occupies a chip area of 0.4mm2 and draws 95 mA from 3V. An array of two PLLs with overlapping tuning ranges using this multiplexer is proposed for high-resolution, high-precision FMCW radar.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

自引率

0.00%

发文量