一种28nm FDSOI CMOS射频脉宽和脉位调制器集成电路

M. Grozing, J. Digel, Thomas Veigel, R. Bieg, Jianxiong Zhang, Simon Brandl, Martin Schmidt, C. Haslach, Daniel Markert, W. Templ
{"title":"一种28nm FDSOI CMOS射频脉宽和脉位调制器集成电路","authors":"M. Grozing, J. Digel, Thomas Veigel, R. Bieg, Jianxiong Zhang, Simon Brandl, Martin Schmidt, C. Haslach, Daniel Markert, W. Templ","doi":"10.1109/NORCHIP.2018.8573465","DOIUrl":null,"url":null,"abstract":"A pulse-width and pulse-position modulator (PWPM) IC for RF carriers from 170 MHz to 2.8 GHz is presented. The IC features a digital 5 bit pulse-width (PW) and 6 bit pulse-center (PC) input interface, updated at the RF carrier frequency, a small arithmetic unit, two delay locked loops with a new phase detector, two phase selectors, CMOS pulse logic and two differential binary RF outputs. At 900 MHz, a 14 MBd 256-QAM (112 Mb/s) signal with an EVM of 1.83 % and an ACLR of -45 dB is shown. At 2016 MHz, an ultra-broadband 504 MBd 16-QAM (2.016 Gb/s) signal with an EVM of 13.5 % and a BER of 1.5·10-4 is demonstrated. The IC is implemented in a 28 nm fully depleted silicon-on-insulator (FDSOI) CMOS technology and runs from a 1.0 V supply. It consumes 38 mW at 900 MHz and 58 mW at 2016 MHz carrier frequency.","PeriodicalId":152077,"journal":{"name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A RF Pulse-Width and Pulse-Position Modulator IC in 28 nm FDSOI CMOS\",\"authors\":\"M. Grozing, J. Digel, Thomas Veigel, R. Bieg, Jianxiong Zhang, Simon Brandl, Martin Schmidt, C. Haslach, Daniel Markert, W. Templ\",\"doi\":\"10.1109/NORCHIP.2018.8573465\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A pulse-width and pulse-position modulator (PWPM) IC for RF carriers from 170 MHz to 2.8 GHz is presented. The IC features a digital 5 bit pulse-width (PW) and 6 bit pulse-center (PC) input interface, updated at the RF carrier frequency, a small arithmetic unit, two delay locked loops with a new phase detector, two phase selectors, CMOS pulse logic and two differential binary RF outputs. At 900 MHz, a 14 MBd 256-QAM (112 Mb/s) signal with an EVM of 1.83 % and an ACLR of -45 dB is shown. At 2016 MHz, an ultra-broadband 504 MBd 16-QAM (2.016 Gb/s) signal with an EVM of 13.5 % and a BER of 1.5·10-4 is demonstrated. The IC is implemented in a 28 nm fully depleted silicon-on-insulator (FDSOI) CMOS technology and runs from a 1.0 V supply. It consumes 38 mW at 900 MHz and 58 mW at 2016 MHz carrier frequency.\",\"PeriodicalId\":152077,\"journal\":{\"name\":\"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NORCHIP.2018.8573465\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NORCHIP.2018.8573465","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9

摘要

提出了一种适用于170 MHz ~ 2.8 GHz射频载波的脉宽脉位调制器(PWPM)集成电路。该IC具有一个数字5位脉冲宽度(PW)和6位脉冲中心(PC)输入接口,以射频载波频率更新,一个小型算术单元,两个带新相位检测器的延迟锁相环,两个相位选择器,CMOS脉冲逻辑和两个差分二进制射频输出。在900 MHz时,显示了14 MBd 256-QAM (112 Mb/s)信号,EVM为1.83%,ACLR为-45 dB。在2016 MHz下,实现了504 MBd 16-QAM (2.016 Gb/s)超宽带信号,EVM为13.5%,误码率为1.5·10-4。该集成电路采用28纳米完全耗尽绝缘体上硅(FDSOI) CMOS技术,并在1.0 V电源下运行。它在900 MHz载波频率下消耗38兆瓦,在2016 MHz载波频率下消耗58兆瓦。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A RF Pulse-Width and Pulse-Position Modulator IC in 28 nm FDSOI CMOS
A pulse-width and pulse-position modulator (PWPM) IC for RF carriers from 170 MHz to 2.8 GHz is presented. The IC features a digital 5 bit pulse-width (PW) and 6 bit pulse-center (PC) input interface, updated at the RF carrier frequency, a small arithmetic unit, two delay locked loops with a new phase detector, two phase selectors, CMOS pulse logic and two differential binary RF outputs. At 900 MHz, a 14 MBd 256-QAM (112 Mb/s) signal with an EVM of 1.83 % and an ACLR of -45 dB is shown. At 2016 MHz, an ultra-broadband 504 MBd 16-QAM (2.016 Gb/s) signal with an EVM of 13.5 % and a BER of 1.5·10-4 is demonstrated. The IC is implemented in a 28 nm fully depleted silicon-on-insulator (FDSOI) CMOS technology and runs from a 1.0 V supply. It consumes 38 mW at 900 MHz and 58 mW at 2016 MHz carrier frequency.
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