A 15-50GHz Multiplexer Circuit in 130nm SiGe BiCMOS Technology for Ultra-Wide Frequency Ramps in FMCW Radar

Abstract

We present a high-speed 2:1 multiplexer for ultra-wideband phase-locked loops (PLL) to be used in FMCW radar systems. The circuit works up to frequencies of 50GHz and allows an instantaneous switching between the outputs of two PLLs. At 30GHz, the measured added phase noise of the MUX is −129.6 dBc/Hz at 1MHz offset, and the input isolation at 30GHz is better than 36dB. The core multiplexer circuit excluding buffers occupies a chip area of 0.03mm2 and draws 22m A from a 3V supply. The whole test chip including input buffers, output buffers and bondpads occupies a chip area of 0.4mm2 and draws 95 mA from 3V. An array of two PLLs with overlapping tuning ranges using this multiplexer is proposed for high-resolution, high-precision FMCW radar.