Design Considerations and Evaluation of a High-Speed SAR ADC

Abstract

We present design and evaluation of an asynchronous, alternating-comparator, 800MS/s SAR ADC. The comparators use continuous calibration to compensate for static input offset voltages. We use a combination of measurements and behavioural modelling to identify two possible causes of limited performance; leakage from the output drives onto the input signal, and dynamic offset voltage in the comparators.