Fault-Tolerant and Energy-Efficient Communication in Mixed-Criticality Networks-on-Chips

We observe a tremendous trend towards mixed-criticality systems, where subsystems of different safety assurance level coexist and interact. In addition, embedded systems are demanded to be efficient in terms of energy consumption to achieve longer operation time with the same battery capacity. This paper introduces a novel architecture for an adaptive time-triggered communication at the chip-level, which addresses the above challenges. In the proposed architecture, time-triggered communication offers safety by establishing temporal and spatial segregation of the communication channels. In addition, adaptivity enables the communication backbone to adapt the injection time of message according to the real execution time of computational tasks, thereby decreasing the overall makespan of the application and increasing the sleep time. In addition to power saving, adaptivity helps to achieve fault recovery, as a faulty subsystem can be shut down and replaced by a backup subsystem. The proposed concept has been evaluated by an example scenario. The results exhibit that using the proposed concept, makespan of the processor and consequently the energy consumption are reduced. In addition to energy, the amount of the used memory for storing the communication schedules is also decreased.