Design of Stacked-MOS Transistor mm-Wave Class C Amplifiers for Doherty Power Amplifiers

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) Pub Date : 2018-10-01 DOI:10.1109/NORCHIP.2018.8573519

M. Montaseri, J. Aikio, T. Rahkonen, A. Pärssinen

引用次数: 1

Abstract

This paper discusses the design requirements of class C auxiliary (aux) amplifiers deployed in Doherty power amplifiers (DPA). Taking conduction angle and back-off (BO) level into account a global design chart is presented which can be utilized to properly dimension the aux amplifier. Based on the proposed method a class C power amplifier is designed and exploited in a DPA circuit at 28GHz which is evaluated using simulations based on 45nm CMOS technology. Simulations reveal 27dBm saturated output power, 60% maximum drain efficiency (DE), 45% DE at 6dBBO, and 2 times efficiency enhancement at 6dB BO which is a new record in this trend.

查看原文本刊更多论文

用于Doherty功率放大器的堆叠mos晶体管毫米波C类放大器的设计

本文讨论了用于Doherty功率放大器(DPA)的C类辅助放大器的设计要求。在考虑导通角和回退电平的情况下，给出了辅助放大器的全局设计框图。基于该方法设计并实现了28GHz DPA电路中的C类功率放大器，并基于45nm CMOS技术进行了仿真评估。仿真结果表明，饱和输出功率为27dBm，最大漏极效率(DE)为60%，6dbbbo时的DE为45%，6dBBO时的效率提高了2倍，这是该趋势的新记录。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

自引率

0.00%

发文量