2010 11th International Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (EuroSimE)最新文献

{"title":"Wafer level packaging (WLP): Fan-in, fan-out and three-dimensional integration","authors":"Xuejun Fan","doi":"10.1109/ESIME.2010.5464548","DOIUrl":"https://doi.org/10.1109/ESIME.2010.5464548","url":null,"abstract":"In this paper, the state-of-the-art results of research and development in wafer-level packaging (WLP) is reviewed. The paper starts from the introduction of several fan-in wafer-level packaging technologies. The focus is given on the fan-in WLP reliability performance as related to the structural differences. New failure mechanisms that appear in build-up stack layers are discussed. Next, emerging fan-out wafer level packaging technologies are introduced. Several key challenges in fan-out WLP technologies are examined. Finally, Three-dimensional (3-D) integration of through-silicon-via (TSV) technology and wafer-level bonding technology with WLP, especially in MEMS and image sensor applications, is discussed.","PeriodicalId":152004,"journal":{"name":"2010 11th International Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126441402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal performance enhancement by exploitation of nano-effects","authors":"B. Wunderle","doi":"10.1109/ESIME.2010.5464506","DOIUrl":"https://doi.org/10.1109/ESIME.2010.5464506","url":null,"abstract":"Thermal interface material resistance is one of the bottlenecks for efficient thermal management. Much research has been undertaken in the last years to overcome the finite thermal conductivity as well as the interface resistance of, above all, polymer-based TIMs varying material parameters such as filler particles material, size and modality as well as matrix material properties.","PeriodicalId":152004,"journal":{"name":"2010 11th International Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114278685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Influence of PCB design and materials on chip solder joint reliability","authors":"M. Berthou, P. Retailleau, H. Frémont, A. Guédon-Gracia, C. Jéphos-Davennel","doi":"10.1109/ESIME.2010.5464569","DOIUrl":"https://doi.org/10.1109/ESIME.2010.5464569","url":null,"abstract":"This paper describes chip solder joint reliability on three substrate types: one board SMI (aluminium substrate) and two different boards in FR4. Several chip sizes and types (resistor, capacitor) were assembled on these boards. Accelerated Thermal cycles (ATC) -55/+125°C were applied to evaluate the lifetime of chip solder joints. The different results obtained showed an important dispersion in Time To Failure (TTF) according to the substrate type. Literature data confirm this dispersion. To understand this discrepancy Finite Element Modelling (FEM) analyses were used to evaluate the influence of PCB design and materials on solder chip component reliability. The simulations permit to identify which parameters are the most influent.","PeriodicalId":152004,"journal":{"name":"2010 11th International Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129076871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Copper pillar bump structure optimization for flip chip packaging with Cu/Low-K stack","authors":"X.R. Zhang, W.H. Zhu, B. P. Liew, M. Gaurav, A. Yeo, K.C. Chan","doi":"10.1109/ESIME.2010.5464565","DOIUrl":"https://doi.org/10.1109/ESIME.2010.5464565","url":null,"abstract":"Copper pillar bumping is a promising solution to cope with the challenges which flip chip packages face when bump pitch size keep shrinking. A large FCBGA(flip chip ball grid array) package for 45nm Cu/Low-K device with Cu pillar bumps is chosen to investigate the package reliability. Finite element models have been built with multi-level sub-modeling technique to consider the detailed Cu/Low-K structure in the chip. Comparison on Cu pillar bumps vs. solder bumps shows the former bump type generated about 20∼30% higher stress on Cu/lowK structure. Thus package reliability may become a concern when Cu pillar is used. To improve the package reliability, design optimization is carried out on Cu pillar bump structure. DOE (design of experiment) study is done on the following factors: Cu pillar height, PI (polyimide) passivation opening and PI thickness etc. Loading is considered for both post flip chip attach process (reflow) and after full assembly (curing). It is found that the stress in post flip chip attach process is much higher than that after full assembly. For Cu/low-K devices, special care is needed for flip chip attach process. Stress on Cu/low-K interface has been analyzed in detail, and it is shown that the interface stress pattern is highly dependent on UBM structure design, especially PI opening and thickness. An overall picture of the PI effect is presented based on optimization results. Lower Cu pillar height, smaller PI opening and higher thickness are recommended for bump structure design.","PeriodicalId":152004,"journal":{"name":"2010 11th International Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134457424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Computer simulation and design of a solder joint vibration test machine","authors":"E. Kamara, Hua Lu, C. Bailey, C. Hunt, D. Di Maio, O. Thomas","doi":"10.1109/ESIME.2010.5464587","DOIUrl":"https://doi.org/10.1109/ESIME.2010.5464587","url":null,"abstract":"Vibration is commonly encountered during the life time of electronic components. It is a major cause of failure due to cyclic strain and stress that give rise to damage in the materials making up the component. The recent move from lead to lead-free soldering by the electronics industry has necessitated the generation of material properties data that will allow accurate prediction of the lead-free solder's performance under vibration conditions. To assess the reliability of lead-free solders under vibration loading, test equipment has been designed for small solder joints using a piezoelectric cell as the vibration source. This equipment will also be used to produce results that can be used to extract solder mechanical material properties and fatigue lifetime parameters suitable for numerical simulations and prediction of solder joint lifetime under vibration loading. This paper focuses on the analysis of the structure of the proposed vibration test equipment using Finite Element analysis method. Modal analysis as well as transient analysis has been undertaken to help understand the equipment response in vibration tests. A number of design variables and loading conditions have been analysed in this work.","PeriodicalId":152004,"journal":{"name":"2010 11th International Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"57 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131958167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An on-chip experimental assessment Of Casimir force effect in micro-electromechanical systems","authors":"R. Ardito, B. de Masi, A. Frangi, A. Corigliano","doi":"10.1109/ESIME.2010.5464555","DOIUrl":"https://doi.org/10.1109/ESIME.2010.5464555","url":null,"abstract":"The influence of Casimir force on the mechanical behaviour of micro-electro-mechanical systems (MEMS) has deserved much attention in the recent scientific literature. This paper reports the outcomes of an experimental test, carried out on a micro-structure which reproduces the essential features of real-life MEMS. The aim of the experiment was to evaluate the effect of Casimir forces between two parallel plates, separated by a sub-micron gap. The results of the tests are critically evaluated by comparison with theoretical predictions, account taken of some peculiar features of Casimir forces for silicon slabs in real MEMS. The obtained results suggest that Casimir force could play an important role for micro and nano devices.","PeriodicalId":152004,"journal":{"name":"2010 11th International Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133767252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The probability design for wire bonding process by finite element and Monte Carlo method","authors":"Huixian Wu, Yangjian Xu, L. Liang, Y. Liu, S. Martin","doi":"10.1109/ESIME.2010.5464529","DOIUrl":"https://doi.org/10.1109/ESIME.2010.5464529","url":null,"abstract":"In this paper, a numerical simulation-based parametric study on wire bonding is implemented by the probability method that combines the response surface strategy and the Monte Carlo random simulation method. The distribution probabilities of the peak stress values in metal and interlayer dielectric (ILD) stack layers are discussed with the variation of free air ball radius, Al pad thickness and ball bonding height in the wire bonding structure and the sensitivities of the output performances to the input variables are assessed. Finally, the major impact factors are determined for optimization of wire bonding.","PeriodicalId":152004,"journal":{"name":"2010 11th International Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117159535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Computational materials engineering: Capabilities of atomic-scale prediction of mechanical, thermal, and electrical properties of microelectronic materials","authors":"A. Mavromaras, D. Rigby, W. Wolf, M. Christensen, M. Halls, C. Freeman, P. Saxe, E. Wimmer","doi":"10.1109/ESIME.2010.5464604","DOIUrl":"https://doi.org/10.1109/ESIME.2010.5464604","url":null,"abstract":"Atomic-scale computational materials engineering offers an exciting complement to experimental observations, revealing critical materials property data, and providing understanding which can form the basis for innovation. This contribution reviews the current state of atomic-scale simulations and their capabilities to predict mechanical, thermal, and electric properties of microelectronics materials. Specific examples are the elastic moduli of compounds such as aluminum oxide, the strength of an aluminum/silicon nitride interface, the first-principles prediction of coefficients of thermal expansion of bulk aluminum and silicon nitride, thermal conductivity of polyethylene, the prediction of the diffusion coefficient of hydrogen in metallic nickel, the calculation of dielectric properties of zinc oxide and optical properties of silicon carbide. The final example illustrates the control of the work function in the HfO2/TiN interface of a CMOS gate stack. For an increasing number of materials properties, computed values possess accuracies similar to measured data. Such accuracy has become possible due to advances in theoretical approaches and numerical algorithms combined with the astounding increase in compute power.","PeriodicalId":152004,"journal":{"name":"2010 11th International Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129299769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Vibration durability of Pb-free HVQFN assemblies","authors":"C. Choi, M. Al-Bassyiouni, A. Dasgupta, J. D. de Vries, W. Balemans, W. V. van Driel","doi":"10.1109/ESIME.2010.5464531","DOIUrl":"https://doi.org/10.1109/ESIME.2010.5464531","url":null,"abstract":"In this paper, the vibration durability of SAC305 solder interconnects of Heat-sink Very-thin Quad Flat-pack No-leads (HVQFN) assemblies is investigated by accelerated stress testing and Physics-of-Failure (PoF) simulations, under various types of vibration excitation. In future work, these results will be used to develop PoF models for vibration fatigue durability of Pb-free SAC305 solder interconnects and to extract model constants from test data.","PeriodicalId":152004,"journal":{"name":"2010 11th International Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122128388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of an elaborate simulation tool for electrochemical failures in microelectronic packages","authors":"M. van Soestbergen, R. Rongen, K. Jansen, W. V. van Driel","doi":"10.1109/ESIME.2010.5464503","DOIUrl":"https://doi.org/10.1109/ESIME.2010.5464503","url":null,"abstract":"The ever increasing complexity and function integration of microelectronic products in combination with the decreasing design margins, the decreasing time-to-market, and ever increasing gap between technology advance and fundamental knowledge opposes a severe challenge for the microelectronics industry to meet the quality, robustness, and reliability requirements of their products. In order to meet these requirements, the reliability of microelectronic products is traditionally assessed using tests at elevated external stimuli, such as temperature, ambient humidity and applied voltage. Recently, the perspective of reliability assessments has shifted towards an approach referred to as knowledge-based qualification, where costumer requirements and operational conditions are translated to stress tests conditions using computer simulations for failure mechanisms and reliability data from corresponding products under comparable conditions. While in the past years simulations tools to predict water absorption and (thermo-)mechanical stresses in packages have been developed, there are no generally accepted simulation tools to predict the effect of electrochemical processes on the performance of products. However, simulation tools that are capable of modelling the electrochemical processes at the interior of packages are indispensable instruments to rigorously study failures due to, e.g., the corrosion of bondpads or the growth of dendritic deposits at metallizations. In this talk a model for the transport of ionic species coupled to a relation for the electrochemical charge transfer rate at electrode is presented. We show results of this model for realistic two-dimensional structures and compare the results with experimental data. We will show that the experimental and model results agree well each other. Additionally, we will show that the model we present can be unequivocally incorporated in the current thermo-mechanical simulation models. Finally, we will address future trends and discuss the perspectives of elaborate simulation tools for the prediction of microelectronics reliability.","PeriodicalId":152004,"journal":{"name":"2010 11th International Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125769828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}