21st International Conference on VLSI Design (VLSID 2008)最新文献_第8页

A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters 一种包含积和和移位的快速算术块的合并合成技术

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.112

Sabyasachi Das, S. Khatri

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引用次数: 2

On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit 采用回转速率监测电路的片上工艺变化检测

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.67

Amlan Ghosh, R. Rao, Jae-Joon Kim, C. Chuang, Richard B. Brown

引用次数: 29

A Robust Level-Shifter Design for Adaptive Voltage Scaling 一种自适应电压标度的鲁棒移电平器设计

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.61

Ankur Gupta, Rajat Chauhan, V. Menezes, V. Narang, H. M. Roopashree

引用次数: 10

Low Power Hardware Architecture for VBSME Using Pixel Truncation 使用像素截断的VBSME低功耗硬件架构

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.100

A. Bahari, T. Arslan, A. Erdogan

引用次数: 6

MPSoC Communication Architecture Exploration Using an Abstraction Refinement Method 基于抽象细化方法的MPSoC通信架构探索

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.64

Hao Shen, F. Pétrot

引用次数: 4

Unified Vdd Vth Optimization Based DVFM Controller for a Logic Block 基于统一Vdd Vth优化的逻辑块DVFM控制器

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.69

S. Kannan, N. S. Sreeram, B. Amrutur

引用次数: 0

0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops 0.35µ，1 GHz，采用数字延时锁环阵列的CMOS时序发生器

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.95

B. Srinivasan, V. Chandratre, Menka Tewani

{"title":"0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops","authors":"B. Srinivasan, V. Chandratre, Menka Tewani","doi":"10.1109/VLSI.2008.95","DOIUrl":"https://doi.org/10.1109/VLSI.2008.95","url":null,"abstract":"This paper describes the architecture and performance of a 0.35 mu, 1 GHZ, CMOS timing generator using array of delay lock loop. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with sub gate delay resolution to be implemented. The proposed delay lock loops uses novel multiplexer based dual phase and frequency detector along with a charge pump where the injected charge approaches zero as the loop approaches lock on the leading edge and the trailing edge of an input clock reference. This greatly reduces the timing jitter, loop locks to both the leading and trailing clock edges as the dual phase and frequency detector along with charge pump converts the phase difference in to voltages. Test results show a timing jitter of less than 20 pS for the DLL (delay lock loop) circuit .The DLL has a dead zone less than 0.01 nS in the phase characteristics and has low phase sensitivity errors. The timing generator is implemented as an array of delay locked loops (Kostamovaara, 2000) which exponentially reduce the locking time. An experimental proto type was simulated at 0.7 mu and 0.35 mu technologies with a supply voltage of 5 V and 3.3 V respectively.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116605238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models 通过多测试序列和应用感知故障模型提高内存成品率

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.115

A. Kokrady, C. Ravikumar, N. Chandrachoodan

{"title":"Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models","authors":"A. Kokrady, C. Ravikumar, N. Chandrachoodan","doi":"10.1109/VLSI.2008.115","DOIUrl":"https://doi.org/10.1109/VLSI.2008.115","url":null,"abstract":"In this paper, we propose a way to improve the yield of memory products by selecting the appropriate test strategy for memory Built- in Self-Test (BIST). We argue that by testing the memory through a sequence of test algorithms which differ in their fault coverage, it is possible to bin the memory into multiple yield bins and increase the yield and product revenue. Further, the test strategy must take into consideration the usage model of the memory. Thus, a number of video and audio buffers are used in sequential access mode, but are overtested using conventional memory test algorithms which model a large number of defects which do not impact the operation of the buffers. We propose a binning strategy where memory test algorithms are applied in different order of strictness such that bins have a specific defect / fault grade. Depending on the applications some of these bins need not be discarded but sold at a lower price as the functionality would never catch the fault due to its usage of memory. We introduce the notion of a test map for the on-chip memories in a SoC and provide results of yield simulation on two specific test strategies called \"Most Strict First\" and \"Least Strict First\". Our simulations indicate that significant improvements in yield are possible through the adoption of the proposed technique. We show that the BIST controller area and run-time overheads also reduce when information about the usage model of the memory, such as sequential access, is exploited.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127187398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips 使用不可靠芯片设计可靠系统的跨层方法

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.135

F. Kurdahi, N. Dutt, A. Eltawil, S. Nassif

{"title":"Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips","authors":"F. Kurdahi, N. Dutt, A. Eltawil, S. Nassif","doi":"10.1109/VLSI.2008.135","DOIUrl":"https://doi.org/10.1109/VLSI.2008.135","url":null,"abstract":"The design for manufacturing and yield (DFM&Y) is fast becoming an indispensable consideration in today's SoCs. Most current flows only consider manufacturability and yield at the lowest levels: process, layout and circuit. As such, these metrics are treated as an afterthought. With advanced process nodes, it has become increasingly expensive-and soon prohibitive-to guarantee bit level error free chips. The challenge now is to design reliable systems using chips that may have some faults. This has lead to approaches that consider DFM&Y at the system level where more benefit can be reaped, and to consider the problem across the design layers. This tutorial covers cross layer approach to design for DFM&Y spanning from the application all the way to manufacturing, overviews various techniques being explored today, and demonstrates its effectiveness on key applications including wireless, multimedia and imaging. We believe that this tutorial will benefit a large percentage of the attendees at VLSI Design 2008, and should elicit an excellent response at the VLSI Design 2008 conference, he tutorial is intended for application designers, chip architects, managers, CAD tool developers, researchers and students interested in System-on-Chip design, platform-based design methodologies, and trends in design for manufacturing and yield at the system level. Attendees should have basic (undergraduate-level) knowledge of VLSI Design and SoC design flows. Familiarity with architectural concepts such as IP based design, and applications such as wireless and multimedia is desirable, but not required. No specific knowledge of CAD tools or modeling languages is required for this tutorial.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127573659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block Using Symmetrized 9T SRAM Cell with Controlled Read 100MHz至1GHz, 0.35V至1.5V供应256 x 64 SRAM块，使用对称的9T SRAM单元与控制读取

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.89

Satish Anand Verkila, Sivakumar Bondada, B. Amrutur

引用次数: 28