21st International Conference on VLSI Design (VLSID 2008)最新文献_第9页

VSI Standards, Current Status and Future Work VSI标准、现状和未来工作

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.142

Kathy Werner

引用次数: 0

GyroCompiler: A Soft IP Model Synthesis and Analysis Framework for Design of MEMS Based Gyroscopes 陀螺编译器:用于MEMS陀螺仪设计的软IP模型综合与分析框架

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.10

S. Jairam, N. Bhat

引用次数: 2

Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS 纳米级CMOS缺陷容限的伪N/PMOS重构

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.104

M. Ashouei, A. Singh, A. Chatterjee

{"title":"Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS","authors":"M. Ashouei, A. Singh, A. Chatterjee","doi":"10.1109/VLSI.2008.104","DOIUrl":"https://doi.org/10.1109/VLSI.2008.104","url":null,"abstract":"End-of-the-roadmap nanoscale CMOS is expected to suffer from significant defectivity due to manufacturing defects, random process variations, and wear-out during normal operational. To ensure acceptable yield and reliable operation of the circuit during its life-time, future circuits must be equipped with significant defect-tolerance capabilities. Traditional defect-tolerance approaches are too expensive to be applied to general purpose circuits. In this paper, we propose a defect-tolerant CMOS logic gate architecture that exploits the inherent functional redundancy in static CMOS. This is accomplished by reconfiguring the CMOS logic gate to a pseudo-NMOS-like gate in the presence of a defect. The resulting defect-tolerant logic architecture incurs only a modest area overhead. The proposed gate design can tolerate defects in either the pull-up or pull-down network of the gate. The architecture can tolerate multiple defects across the logic gates of a CMOS logic circuit. The effectiveness of the proposed defect tolerance technique and its impact on circuit delay and power is studied. It is shown that the technique imposes little delay overhead (less than 6%) but incurs power dissipation overhead (less than 20%) in the presence of defects.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126739860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Single Chip Encryptor/Decryptor Core Implementation of AES Algorithm 单片加密/解密核心实现AES算法

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.82

Monjur Alam, Santosh K. Ghosh, D. R. Chowdhury, I. Sengupta

引用次数: 9

Highly Linear Wide Dynamic Swing CMOS Transconductance Multiplier Using Source-Degeneration V-I Converters 采用源退化V-I变换器的高线性宽动态摆CMOS跨导倍增器

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.91

S. Garimella

引用次数: 3

Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations 电压和温度可扩展的门延迟和转换模型，包括门内变化

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.92

B. P. Das, Janakiraman Viraraghavan, B. Amrutur, H. S. Jamadagni, N. Arvind

引用次数: 8

PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors PTSMT: SMT处理器的跨能级功率、性能和热研究工具

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.84

D. Kannan, Aseem Gupta, Aviral Shrivastava, N. Dutt, F. Kurdahi

{"title":"PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors","authors":"D. Kannan, Aseem Gupta, Aviral Shrivastava, N. Dutt, F. Kurdahi","doi":"10.1109/VLSI.2008.84","DOIUrl":"https://doi.org/10.1109/VLSI.2008.84","url":null,"abstract":"Simultaneous Multi-Threading (SMT) processors are becoming popular because they exploit both instruction-level and thread- level parallelism by issuing instructions from different threads in the same cycle. However, the issues of power and thermal management hinder SMT processors fabricated in nano-scale technologies. Power and thermal issues in SMT processors not only limit the achievable performance, but also have a direct impact on the cost and viability of these processors. While several performance simulation tools to explore the performance aspect of SMT processors early in their design phase exist, there is a lack of early power and performance evaluation tools for SMT processors. To this end, we have developed PTSMT: a tightly coupled power, performance and thermal exploration tool for SMT processors. In this paper, we demonstrate that PTSMT can automatically and effectively accomplish power, performance and thermal exploration of SMT processors at various levels of design hierarchy, at the application level, microarchitecture level, and physical level. Our experimental results show that: at the application level, number of contexts into which an application is divided could affect performance by 2.2times, energy by 52%, and peak temperature by 35degC; and at the microarchitecture level, context swapping during run time could reduce energy by 9% and improve performance by 8%. These observations indicate the size of the design space which can be explored using PTSMT.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132011568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Concurrent Multi-Dimensional Adaptation for Low-Power Operation in Wireless Devices 无线设备低功耗运行的并发多维自适应

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.101

R. Senguttuvan, Shreyas Sen, A. Chatterjee

引用次数: 3

Delay and Energy Efficient Design of On-Chip Encoded Bus with Repeaters 带中继器的片上编码总线的延迟和节能设计

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.21

Qingli Zhang, Jinxiang Wang, Y. Ye

引用次数: 3

Energy-Efficient Soft-Error Protection Using Operand Encoding and Operation Bypass 基于操作数编码和操作旁路的节能软错误保护

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.116

K. Gandhi, N. Mahapatra

引用次数: 3