21st International Conference on VLSI Design (VLSID 2008)最新文献

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Memory Design and Advanced Semiconductor Technology 存储器设计与先进半导体技术
21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-02-12 DOI: 10.1109/VLSI.2008.133
D. Harame, S. Iyer, J. Watts, R. Joshi, J. Barth
{"title":"Memory Design and Advanced Semiconductor Technology","authors":"D. Harame, S. Iyer, J. Watts, R. Joshi, J. Barth","doi":"10.1109/VLSI.2008.133","DOIUrl":"https://doi.org/10.1109/VLSI.2008.133","url":null,"abstract":"This tutorial will provide a bottom-up view of the changes in semiconductor memory design as we move into the nanometer regime. We begin by discussing the breakdown of scaling and the power problem. As innovation replaces classical scaling we investigate the use of stress engineering to improve device level performance. Technology challenges in lithography and interconnects are addressed. The consequences of innovation and scaling on RF/Analog characteristics must also be considered. The scaling of memory presents yet another challenge. We proceed to discuss the modeling of these effects for the circuit designer including discussion of the many new and traditional sources of variation. We describe how these are characterized how they can be controlled by layout rules and how the remaining variation can be describe in the model to enable Statistical Timing and other advanced circuit techniques. At the circuit level we consider in detail embedded DRAM and SRAM design for both bulk and SOI. We discuss the benefits and challenges of advanced technologies including methods for creating robust designs in the presence of manufacturing variation. We also discuss the design innovations required to utilize advanced technologies for overcoming the \"memory wall\", \"power wall\" and \"ILP wall\".","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115719344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficient Linear Macromodeling via Discrete-Time Time-Domain Vector Fitting 基于离散时间时域向量拟合的高效线性宏建模
21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.12
Chi-Un Lei, N. Wong
{"title":"Efficient Linear Macromodeling via Discrete-Time Time-Domain Vector Fitting","authors":"Chi-Un Lei, N. Wong","doi":"10.1109/VLSI.2008.12","DOIUrl":"https://doi.org/10.1109/VLSI.2008.12","url":null,"abstract":"We present a discrete-time time-domain vector fitting algorithm, called TD-VFz, for rational function macromodeling of port-to-port responses with discrete time-sampled data. The core routine involves a two-step pole refinement process based on a linear least-squares solve and an eigenvalue problem. Applications in the macromodeling of practical circuits demonstrate that TD-VFz exhibits fast computation, excellent accuracy, and robustness against noisy data. We also utilize an quasi-error bound unique to the discrete-time setting to facilitate the determination of approximant model order.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116695699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Architecture Exploration for Low Power Design 低功耗设计的建筑探索
21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.132
V. Kathail, T. Miller
{"title":"Architecture Exploration for Low Power Design","authors":"V. Kathail, T. Miller","doi":"10.1109/VLSI.2008.132","DOIUrl":"https://doi.org/10.1109/VLSI.2008.132","url":null,"abstract":"This tutorial will describe in detail and demonstrate an ESL design flow for architectural exploration to determine low power designs. Increasingly SoC design is driven by integrated mobile devices such as cell phones, music players and hand-held game consoles. These devices rely on standard algorithms such as H.264, 802.1 In, or JPEG2000, which allow room for innovative implementations that can result in differentiated products. An ESL design-flow that integrates application engine synthesis with an industry-leading RTL power estimation technology, such as Sequence Power Theater, enables a designer to explore multiple algorithms and architectures with different power profiles to determine the optimal algorithm-architecture combination in a very short period of time.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124816165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the Use of Hash Tables for Efficient Analog Circuit Synthesis 哈希表在模拟电路合成中的应用
21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.35
Almitra Pradhan, R. Vemuri
{"title":"On the Use of Hash Tables for Efficient Analog Circuit Synthesis","authors":"Almitra Pradhan, R. Vemuri","doi":"10.1109/VLSI.2008.35","DOIUrl":"https://doi.org/10.1109/VLSI.2008.35","url":null,"abstract":"Achieving accurate and speedy circuit sizing is a challenge in automated analog synthesis. System matrix model based estimators predict circuit performance accurately. In this paper we employ hashing in conjunction with matrix models for faster synthesis convergence. With hash tables some matrix element recomputations are avoided, thus improving synthesis time. Hashing is effectively performed by dividing matrix elements into classes and building class-wise hash tables. Hash tables are updated over several synthesis runs which further expedites convergence. Experimental results show that the proposed method can provide 4x-6x speedup over that offered by synthesis approaches employing macromodels but no hashing.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124824706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Power Management of Interactive 3D Games Using Frame Structures 使用框架结构的交互式3D游戏的电源管理
21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.102
Yan Gu, S. Chakraborty
{"title":"Power Management of Interactive 3D Games Using Frame Structures","authors":"Yan Gu, S. Chakraborty","doi":"10.1109/VLSI.2008.102","DOIUrl":"https://doi.org/10.1109/VLSI.2008.102","url":null,"abstract":"We propose a novel dynamic voltage scaling (DVS) scheme that is specifically directed towards 3D graphics- intensive interactive game applications running on battery-operated portable devices. The key to this DVS scheme lies in parsing each game frame to estimate its rendering workload and then using such an estimate to scale the voltage/frequency of the underlying processor. The main novelty of this scheme stems from the fact that game frames offer a rich variety of \"structural\" information (e.g. number of brush and alias models, texture information and light maps) which can be exploited to estimate their processing workload. Although DVS has been extensively applied to video decoding applications, compressed video frames do not offer any information (beyond the frame types - I, B or P) that can be used in a similar manner to estimate their processing workload. As a result, DVS algorithms designed for video decoding mostly rely on control-theoretic feedback mechanisms, where the workload of a frame is predicted from the workloads of the previously-rendered frames. We show that compared to such history-based predictors, our proposed scheme performs significantly better for game applications. Our experimental results, based on the Quake II game engine running on Windows XP, show that for the same energy consumption our scheme results in more than 50% improvement in quality (measured in terms of number of frames meeting their deadlines) compared to history-based prediction schemes.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123763146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
Single Error Correcting Finite Field Multipliers Over GF(2m) GF(2m)上的单误差校正有限域乘法器
21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.105
J. Mathew, C. Argyrides, A. Jabir, H. Rahaman, D. Pradhan
{"title":"Single Error Correcting Finite Field Multipliers Over GF(2m)","authors":"J. Mathew, C. Argyrides, A. Jabir, H. Rahaman, D. Pradhan","doi":"10.1109/VLSI.2008.105","DOIUrl":"https://doi.org/10.1109/VLSI.2008.105","url":null,"abstract":"This paper presents a new method for designing single error correcting Galois field multipliers over polynomial basis. The proposed method uses multiple parity prediction circuits to detect and correct logic errors and gives 100% fault coverage both in the functional unit and the parity prediction circuitry. Area, power and delay overhead for the proposed design technique is analyzed. It is found that compared to the traditional triple modular redundancy (TMR) techniques for single error correction the proposed technique is very cost efficient.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115575356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
On Common-Mode Skewed-Load and Broadside Tests 关于共模偏载和舷侧试验
21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.16
I. Pomeranz, S. Reddy, S. Kundu
{"title":"On Common-Mode Skewed-Load and Broadside Tests","authors":"I. Pomeranz, S. Reddy, S. Kundu","doi":"10.1109/VLSI.2008.16","DOIUrl":"https://doi.org/10.1109/VLSI.2008.16","url":null,"abstract":"Two-pattern tests for delay faults in standard scan circuits can be of one of two types: skewed-load or broadside. Each type of tests creates different conditions during test application due to the different way in which scan mode and functional mode are interleaved. Therefore, tests that are applicable both as skewed-load tests and as broadside tests are useful for comparing the two types of tests with respect to properties such as defect coverage or overtesting. In this work we investigate the possibility of generating tests that are applicable under both test application schemes. We refer to two-pattern tests that are applicable as both skewed-load and broadside tests as common-mode tests. We show that most benchmark circuits have sufficient numbers of common-mode tests to make them an interesting class of tests. Moreover, we show that the use of multiple scan chains increases the number of common-mode tests.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128224250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Oversampling Analog-to-Digital Converter Design 过采样模数转换器设计
21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.130
S. Pavan, N. Krishnapura
{"title":"Oversampling Analog-to-Digital Converter Design","authors":"S. Pavan, N. Krishnapura","doi":"10.1109/VLSI.2008.130","DOIUrl":"https://doi.org/10.1109/VLSI.2008.130","url":null,"abstract":"Summary form only given. Analog-to-digital converters (or sigma-delta) converters have now become routine aspects of high- performance signal processing, ranging from precision audio to RF transceivers. In this tutorial, we will present, in a systematic fashion, the basics and design aspects of delta-sigma data converters, along with a case study of a high performance ADC designed for digital audio. The intended audience is analog/mixed signal designers with limited prior exposure to over sampling converters and graduate students. Anyone interested in designing, simulating and testing such converters should benefit greatly by attending this tutorial.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114525473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
NBTI Degradation: A Problem or a Scare? NBTI退化:问题还是恐惧?
21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.43
K. Saluja, Shriram Vijayakumar, Warin Sootkaneung, Xaingning Yang
{"title":"NBTI Degradation: A Problem or a Scare?","authors":"K. Saluja, Shriram Vijayakumar, Warin Sootkaneung, Xaingning Yang","doi":"10.1109/VLSI.2008.43","DOIUrl":"https://doi.org/10.1109/VLSI.2008.43","url":null,"abstract":"Negative bias temperature instability (NBTI) has been identified as a major and critical reliability issue for PMOS devices in nano-scale designs. It manifests as a negative threshold voltage shift, thereby degrading the performance of the PMOS devices over the lifetime of a circuit. In order to determine the quantitative impact of this phenomenon an accurate and tractable model is needed. In this paper we explore a novel and practical methodology for modeling NBTI degradation at the logic level for digital circuits. Its major contributions include i) a SPICE level simulation to identify stress on PMOS devices under varying input conditions for various gate types and ii) a gate level simulation methodology that is scalable and accurate for determining stress on large circuits. We validate the proposed logic level simulation methodology by showing that it is accurate within 1% of the reference model. Contrary to many other papers in this area, our experimental results show that the overall delay degradation of large digital circuits due to NBTI is relatively small.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125709402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning 基于精英非支配排序的超大规模集成电路平面规划中面积和长度同时最小化的遗传算法
21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.97
Pradeep Fernando, S. Katkoori
{"title":"An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning","authors":"Pradeep Fernando, S. Katkoori","doi":"10.1109/VLSI.2008.97","DOIUrl":"https://doi.org/10.1109/VLSI.2008.97","url":null,"abstract":"VLSI floor-planning in the gigascale era must deal with multiple objectives including wiring congestion, performance and reliability. Genetic algorithms lend themselves naturally to multi-objective optimization. In this paper, a multi-objective genetic algorithm is proposed for floorplanning that simultaneously minimizes area and total wirelength. The proposed genetic floorplanner is the first to use non-domination concepts to rank solutions. Two novel crossover operators are presented that build floorplans using good sub-floorplans. The efficiency of the proposed approach is illustrated by the 18% wirelength savings and 4.6% area savings obtained for the GSRC benchmarks and 26% wirelength savings for the MCNC benchmarks for a marginal 1.3% increase in area when compared to previous floorplanners that perform simultaneous area and wirelength minimization.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132905854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
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