{"title":"On the Use of Hash Tables for Efficient Analog Circuit Synthesis","authors":"Almitra Pradhan, R. Vemuri","doi":"10.1109/VLSI.2008.35","DOIUrl":null,"url":null,"abstract":"Achieving accurate and speedy circuit sizing is a challenge in automated analog synthesis. System matrix model based estimators predict circuit performance accurately. In this paper we employ hashing in conjunction with matrix models for faster synthesis convergence. With hash tables some matrix element recomputations are avoided, thus improving synthesis time. Hashing is effectively performed by dividing matrix elements into classes and building class-wise hash tables. Hash tables are updated over several synthesis runs which further expedites convergence. Experimental results show that the proposed method can provide 4x-6x speedup over that offered by synthesis approaches employing macromodels but no hashing.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"21st International Conference on VLSI Design (VLSID 2008)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI.2008.35","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
Achieving accurate and speedy circuit sizing is a challenge in automated analog synthesis. System matrix model based estimators predict circuit performance accurately. In this paper we employ hashing in conjunction with matrix models for faster synthesis convergence. With hash tables some matrix element recomputations are avoided, thus improving synthesis time. Hashing is effectively performed by dividing matrix elements into classes and building class-wise hash tables. Hash tables are updated over several synthesis runs which further expedites convergence. Experimental results show that the proposed method can provide 4x-6x speedup over that offered by synthesis approaches employing macromodels but no hashing.