21st International Conference on VLSI Design (VLSID 2008)最新文献_第2页

A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits 时延约束寄存器传输级顺序电路的鲁棒自顶向下动态功率估计方法

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.56

Sriram Sambamurthy, J. Abraham, R. Tupuri

{"title":"A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits","authors":"Sriram Sambamurthy, J. Abraham, R. Tupuri","doi":"10.1109/VLSI.2008.56","DOIUrl":"https://doi.org/10.1109/VLSI.2008.56","url":null,"abstract":"We present a top-down dynamic power estimation methodology for delay constrained sequential circuits. The methodology works at the register transfer level (RT-Level), and applies to both structural and behavioral descriptions of circuits. The average power consumption of a circuit varies with the worst case cycle-time or frequency of operation. As the cycle-time is reduced, the increase in the capacitance of the circuit due to technology mapping and optimization is captured by our technique at the RT-Level using the principles of logical effort. Switching activity is obtained at the RT-Level visible nodes through RT-Level functional simulation. This information is utilized to approximate the activities at the remaining nodes of the circuit and combined with capacitance to estimate dynamic power. Power estimation results for RT-Level sequential circuits indicate good accuracy (average error<10%) with respect to the reference values obtained by detailed gate-level power analysis. The power consumed by a circuit varies with the target library and technology. Our methodology is parameterizable and the results obtained for different target libraries at 0.18 mum TSMC and 0.13 mum UMC technologies are consistent, indicating the robustness of our technique. The applicability of our methodology in design frameworks consisting of bottom-up techniques is also discussed.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132269756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Scan Delay Testing of Nanometer SoCs 纳米soc的扫描延迟测试

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.134

A. Singh

引用次数: 3

Threshold Voltage Control through Multiple Supply Voltages for Power-Efficient FinFET Interconnects 通过多电源电压控制低功耗FinFET互连的阈值电压

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.117

Anish Muttreja, Prateek Mishra, N. Jha

引用次数: 17

Energy-Efficient, High Performance Circuits for Arithmetic Units 高能效、高性能算术单元电路

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.49

S. Agarwal, K. PavankumarV., R. Yokesh

{"title":"Energy-Efficient, High Performance Circuits for Arithmetic Units","authors":"S. Agarwal, K. PavankumarV., R. Yokesh","doi":"10.1109/VLSI.2008.49","DOIUrl":"https://doi.org/10.1109/VLSI.2008.49","url":null,"abstract":"Adders and multipliers are the most important arithmetic units in a general microprocessor and the major source of power dissipation. Various architecture styles exist to implement these units, each having their own merits and demerits. However, due to continuing integrating intensity and growing needs of portable devices, low power design is of prime importance. In addition, much power is dissipated due to a large number of spurious transitions on internal nodes in power hungry multiplier structures. We present a new full adder structure based on complementary pass transistor logic (CPL) which is faster and more energy efficient than the existing structures. We also propose a new technique of implementing multiplier circuit using decomposition logic which improves speed and reduces power consumption by reducing the spurious transitions on internal nodes. Combined with the new adder structure and the decomposition logic, there is substantial improvement in the performance of the multiplier structures. With the help of these state of the art designs, it would be possible to design highly power efficient processors, especially digital signal processors. We have used TSPICE for simulation in the TSMC 180 nm technology.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127066225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 42

Industry Standards from Accellera Accellera的行业标准

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.123

S. Mehta

引用次数: 3

A New Approach for Estimation of On-Resistance and Current Distribution in Power Array Layouts 功率阵列布局中导通电阻和电流分布估计的新方法

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.87

J. Ghosh, S. Mukhopadhyay, A. Patra, B. Culpepper, Tawen Mei

引用次数: 2

Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies 亚100纳米PDSOI和双栅技术的最佳双vt设计

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.50

A. Bansal, Jae-Joon Kim, Keunwoo Kim, S. Mukhopadhyay, C. Chuang, K. Roy

引用次数: 2

A Power Efficient Approach to Fault-Tolerant Register File Design 一种低功耗的容错寄存器文件设计方法

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.53

Mojtaba Amiri-Kamalabad, S. Miremadi, M. Fazeli

引用次数: 1

An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products 一种基于反演的面积与功耗高效算术积和综合方法

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.18

Sabyasachi Das, S. Khatri

{"title":"An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products","authors":"Sabyasachi Das, S. Khatri","doi":"10.1109/VLSI.2008.18","DOIUrl":"https://doi.org/10.1109/VLSI.2008.18","url":null,"abstract":"In state-of-the-art digital signal processing (DSP) and graphics applications, the arithmetic sum-of-product (SOP) is an important and computationally intensive operation, consuming a significant amount of area, delay and power. This paper presents a new algorithmic approach to synthesize a non-timing critical SOP block in an area-efficient and power-efficient way, which can be very useful to reduce the size and power consumption of the non timing-critical portion in the design. We have divided the problem of generating the SOP into three parts: inversion-based creation of the BitClusters (sets of individual partial-product bits, which belong to the ith bitslice), propagation-based reduction of the BitClusters and selective-inversion based computation of the final sum result. Techniques used in these three steps help to reduce the implementation area and power consumption for the SOP block. Our experimental data shows that the SOP block generated by our approach is significantly smaller (8.59% on average) and marginally faster (0.42% on average) than the SOP block generated by a commercially available best-in-class datapath synthesis tool. In addition, our proposed SOP netlist consumes significantly less dynamic power (7.92% on average) and leakage power (5.65% on average) than the netlist generated by the synthesis tool. These improvements were verified on placed-and-routed designs as well.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122221972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A Modeling of a Dynamically Reconfigurable Processor Using SystemC 基于SystemC的动态可重构处理器建模

21st International Conference on VLSI Design (VLSID 2008) Pub Date : 2008-01-04 DOI: 10.1109/VLSI.2008.13

J. Kitamichi, K. Ueda, Kenichi Kuroda

引用次数: 3